dds.hier_info

这是一个用vhdl语言实现dds的例子

|dds
out[0] <= rom01:inst1.q[0]
out[1] <= rom01:inst1.q[1]
out[2] <= rom01:inst1.q[2]
out[3] <= rom01:inst1.q[3]
out[4] <= rom01:inst1.q[4]
out[5] <= rom01:inst1.q[5]
out[6] <= rom01:inst1.q[6]
out[7] <= rom01:inst1.q[7]
out[8] <= rom01:inst1.q[8]
out[9] <= rom01:inst1.q[9]
clk => rom01:inst1.clock
clk => add:inst.clk
m[0] => add:inst.m[0]
m[1] => add:inst.m[1]
m[2] => add:inst.m[2]
m[3] => add:inst.m[3]
m[4] => add:inst.m[4]
m[5] => add:inst.m[5]
m[6] => add:inst.m[6]
m[7] => add:inst.m[7]


|dds|rom01:inst1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]


|dds|rom01:inst1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_t431:auto_generated.address_a[0]
address_a[1] => altsyncram_t431:auto_generated.address_a[1]
address_a[2] => altsyncram_t431:auto_generated.address_a[2]
address_a[3] => altsyncram_t431:auto_generated.address_a[3]
address_a[4] => altsyncram_t431:auto_generated.address_a[4]
address_a[5] => altsyncram_t431:auto_generated.address_a[5]
address_a[6] => altsyncram_t431:auto_generated.address_a[6]
address_a[7] => altsyncram_t431:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_t431:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_t431:auto_generated.q_a[0]
q_a[1] <= altsyncram_t431:auto_generated.q_a[1]
q_a[2] <= altsyncram_t431:auto_generated.q_a[2]
q_a[3] <= altsyncram_t431:auto_generated.q_a[3]
q_a[4] <= altsyncram_t431:auto_generated.q_a[4]
q_a[5] <= altsyncram_t431:auto_generated.q_a[5]
q_a[6] <= altsyncram_t431:auto_generated.q_a[6]
q_a[7] <= altsyncram_t431:auto_generated.q_a[7]
q_a[8] <= altsyncram_t431:auto_generated.q_a[8]
q_a[9] <= altsyncram_t431:auto_generated.q_a[9]
q_b[0] <= <GND>


|dds|rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT


|dds|add:inst
clk => adda[0]~reg0.CLK
clk => adda[1]~reg0.CLK
clk => adda[2]~reg0.CLK
clk => adda[3]~reg0.CLK
clk => adda[4]~reg0.CLK
clk => adda[5]~reg0.CLK
clk => adda[6]~reg0.CLK
clk => adda[7]~reg0.CLK
clk => back[0]~reg0.CLK
clk => back[1]~reg0.CLK
clk => back[2]~reg0.CLK
clk => back[3]~reg0.CLK
clk => back[4]~reg0.CLK
clk => back[5]~reg0.CLK
clk => back[6]~reg0.CLK
clk => back[7]~reg0.CLK
clk => back[8]~reg0.CLK
clk => back[9]~reg0.CLK
clk => back[10]~reg0.CLK
clk => back[11]~reg0.CLK
clk => back[12]~reg0.CLK
clk => back[13]~reg0.CLK
clk => back[14]~reg0.CLK
clk => back[15]~reg0.CLK
adds[0] => Add0.IN24
adds[1] => Add0.IN23
adds[2] => Add0.IN22
adds[3] => Add0.IN21
adds[4] => Add0.IN20
adds[5] => Add0.IN19
adds[6] => Add0.IN18
adds[7] => Add0.IN17
adds[8] => Add0.IN16
adds[9] => Add0.IN15
adds[10] => Add0.IN14
adds[11] => Add0.IN13
adds[12] => Add0.IN12
adds[13] => Add0.IN11
adds[14] => Add0.IN10
adds[15] => Add0.IN9
m[0] => Add0.IN32
m[1] => Add0.IN31
m[2] => Add0.IN30
m[3] => Add0.IN29
m[4] => Add0.IN28
m[5] => Add0.IN27
m[6] => Add0.IN26
m[7] => Add0.IN25
back[0] <= back[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[1] <= back[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[2] <= back[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[3] <= back[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[4] <= back[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[5] <= back[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[6] <= back[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[7] <= back[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[8] <= back[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[9] <= back[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[10] <= back[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[11] <= back[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[12] <= back[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[13] <= back[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[14] <= back[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
back[15] <= back[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adda[0] <= adda[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adda[1] <= adda[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adda[2] <= adda[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adda[3] <= adda[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adda[4] <= adda[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adda[5] <= adda[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adda[6] <= adda[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adda[7] <= adda[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE