📄 dds.tan.qmsg

📁 这是一个用vhdl语言实现dds的例子
💻 QMSG
📖 第 1 页 / 共 3 页
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk memory memory rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|ram_block1a0~porta_address_reg0 rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[0\] 180.05 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 180.05 MHz between source memory \"rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|ram_block1a0~porta_address_reg0\" and destination memory \"rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.777 ns 2.777 ns 5.554 ns " "Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X27_Y9 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X27_Y9; Fanout = 10; MEM Node = 'rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[0\] 2 MEM M4K_X27_Y9 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X27_Y9; Fanout = 1; MEM Node = 'rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.641 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.641 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.641 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.848 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.804 ns) + CELL(0.815 ns) 2.848 ns rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[0\] 3 MEM M4K_X27_Y9 1 " "Info: 3: + IC(0.804 ns) + CELL(0.815 ns) = 2.848 ns; Loc. = M4K_X27_Y9; Fanout = 1; MEM Node = 'rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.619 ns" { clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 66.89 % ) " "Info: Total cell delay = 1.905 ns ( 66.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.943 ns ( 33.11 % ) " "Info: Total interconnect delay = 0.943 ns ( 33.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.848 ns" { clk clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.848 ns" { clk clk~combout clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.868 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.804 ns) + CELL(0.835 ns) 2.868 ns rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M4K_X27_Y9 10 " "Info: 3: + IC(0.804 ns) + CELL(0.835 ns) = 2.868 ns; Loc. = M4K_X27_Y9; Fanout = 10; MEM Node = 'rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.639 ns" { clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 67.12 % ) " "Info: Total cell delay = 1.925 ns ( 67.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.943 ns ( 32.88 % ) " "Info: Total interconnect delay = 0.943 ns ( 32.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.868 ns" { clk clk~combout clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.848 ns" { clk clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.848 ns" { clk clk~combout clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.868 ns" { clk clk~combout clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.835ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.641 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.641 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.848 ns" { clk clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.848 ns" { clk clk~combout clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.868 ns" { clk clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.868 ns" { clk clk~combout clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.835ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[0] } { 0.000ns } { 0.109ns } } } { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 40 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "add:inst\|back\[15\] m\[4\] clk 6.726 ns register " "Info: tsu for register \"add:inst\|back\[15\]\" (data pin = \"m\[4\]\", clock pin = \"clk\") is 6.726 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.539 ns + Longest pin register " "Info: + Longest pin to register delay is 9.539 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns m\[4\] 1 PIN PIN_99 2 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_99; Fanout = 2; PIN Node = 'm\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { m[4] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 344 232 400 360 "m\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.405 ns) + CELL(0.621 ns) 7.961 ns add:inst\|back\[4\]~84 2 COMB LCCOMB_X29_Y9_N8 2 " "Info: 2: + IC(6.405 ns) + CELL(0.621 ns) = 7.961 ns; Loc. = LCCOMB_X29_Y9_N8; Fanout = 2; COMB Node = 'add:inst\|back\[4\]~84'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.026 ns" { m[4] add:inst|back[4]~84 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.047 ns add:inst\|back\[5\]~85 3 COMB LCCOMB_X29_Y9_N10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 8.047 ns; Loc. = LCCOMB_X29_Y9_N10; Fanout = 2; COMB Node = 'add:inst\|back\[5\]~85'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[4]~84 add:inst|back[5]~85 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.133 ns add:inst\|back\[6\]~86 4 COMB LCCOMB_X29_Y9_N12 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 8.133 ns; Loc. = LCCOMB_X29_Y9_N12; Fanout = 2; COMB Node = 'add:inst\|back\[6\]~86'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[5]~85 add:inst|back[6]~86 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 8.323 ns add:inst\|back\[7\]~87 5 COMB LCCOMB_X29_Y9_N14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.190 ns) = 8.323 ns; Loc. = LCCOMB_X29_Y9_N14; Fanout = 2; COMB Node = 'add:inst\|back\[7\]~87'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { add:inst|back[6]~86 add:inst|back[7]~87 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.409 ns add:inst\|back\[8\]~88 6 COMB LCCOMB_X29_Y9_N16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 8.409 ns; Loc. = LCCOMB_X29_Y9_N16; Fanout = 2; COMB Node = 'add:inst\|back\[8\]~88'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[7]~87 add:inst|back[8]~88 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.495 ns add:inst\|back\[9\]~89 7 COMB LCCOMB_X29_Y9_N18 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 8.495 ns; Loc. = LCCOMB_X29_Y9_N18; Fanout = 2; COMB Node = 'add:inst\|back\[9\]~89'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[8]~88 add:inst|back[9]~89 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.581 ns add:inst\|back\[10\]~90 8 COMB LCCOMB_X29_Y9_N20 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 8.581 ns; Loc. = LCCOMB_X29_Y9_N20; Fanout = 2; COMB Node = 'add:inst\|back\[10\]~90'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[9]~89 add:inst|back[10]~90 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.667 ns add:inst\|back\[11\]~91 9 COMB LCCOMB_X29_Y9_N22 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 8.667 ns; Loc. = LCCOMB_X29_Y9_N22; Fanout = 2; COMB Node = 'add:inst\|back\[11\]~91'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[10]~90 add:inst|back[11]~91 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.753 ns add:inst\|back\[12\]~92 10 COMB LCCOMB_X29_Y9_N24 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 8.753 ns; Loc. = LCCOMB_X29_Y9_N24; Fanout = 2; COMB Node = 'add:inst\|back\[12\]~92'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[11]~91 add:inst|back[12]~92 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.839 ns add:inst\|back\[13\]~93 11 COMB LCCOMB_X29_Y9_N26 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 8.839 ns; Loc. = LCCOMB_X29_Y9_N26; Fanout = 2; COMB Node = 'add:inst\|back\[13\]~93'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[12]~92 add:inst|back[13]~93 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.925 ns add:inst\|back\[14\]~94 12 COMB LCCOMB_X29_Y9_N28 1 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 8.925 ns; Loc. = LCCOMB_X29_Y9_N28; Fanout = 1; COMB Node = 'add:inst\|back\[14\]~94'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { add:inst|back[13]~93 add:inst|back[14]~94 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 9.431 ns add:inst\|back\[15\]~71 13 COMB LCCOMB_X29_Y9_N30 1 " "Info: 13: + IC(0.000 ns) + CELL(0.506 ns) = 9.431 ns; Loc. = LCCOMB_X29_Y9_N30; Fanout = 1; COMB Node = 'add:inst\|back\[15\]~71'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { add:inst|back[14]~94 add:inst|back[15]~71 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.539 ns add:inst\|back\[15\] 14 REG LCFF_X29_Y9_N31 2 " "Info: 14: + IC(0.000 ns) + CELL(0.108 ns) = 9.539 ns; Loc. = LCFF_X29_Y9_N31; Fanout = 2; REG Node = 'add:inst\|back\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { add:inst|back[15]~71 add:inst|back[15] } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.134 ns ( 32.85 % ) " "Info: Total cell delay = 3.134 ns ( 32.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.405 ns ( 67.15 % ) " "Info: Total interconnect delay = 6.405 ns ( 67.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.539 ns" { m[4] add:inst|back[4]~84 add:inst|back[5]~85 add:inst|back[6]~86 add:inst|back[7]~87 add:inst|back[8]~88 add:inst|back[9]~89 add:inst|back[10]~90 add:inst|back[11]~91 add:inst|back[12]~92 add:inst|back[13]~93 add:inst|back[14]~94 add:inst|back[15]~71 add:inst|back[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.539 ns" { m[4] m[4]~combout add:inst|back[4]~84 add:inst|back[5]~85 add:inst|back[6]~86 add:inst|back[7]~87 add:inst|back[8]~88 add:inst|back[9]~89 add:inst|back[10]~90 add:inst|back[11]~91 add:inst|back[12]~92 add:inst|back[13]~93 add:inst|back[14]~94 add:inst|back[15]~71 add:inst|back[15] } { 0.000ns 0.000ns 6.405ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.935ns 0.621ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.773 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.773 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.878 ns) + CELL(0.666 ns) 2.773 ns add:inst\|back\[15\] 3 REG LCFF_X29_Y9_N31 2 " "Info: 3: + IC(0.878 ns) + CELL(0.666 ns) = 2.773 ns; Loc. = LCFF_X29_Y9_N31; Fanout = 2; REG Node = 'add:inst\|back\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.544 ns" { clk~clkctrl add:inst|back[15] } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.32 % ) " "Info: Total cell delay = 1.756 ns ( 63.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.017 ns ( 36.68 % ) " "Info: Total interconnect delay = 1.017 ns ( 36.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.773 ns" { clk clk~clkctrl add:inst|back[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.773 ns" { clk clk~combout clk~clkctrl add:inst|back[15] } { 0.000ns 0.000ns 0.139ns 0.878ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.539 ns" { m[4] add:inst|back[4]~84 add:inst|back[5]~85 add:inst|back[6]~86 add:inst|back[7]~87 add:inst|back[8]~88 add:inst|back[9]~89 add:inst|back[10]~90 add:inst|back[11]~91 add:inst|back[12]~92 add:inst|back[13]~93 add:inst|back[14]~94 add:inst|back[15]~71 add:inst|back[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.539 ns" { m[4] m[4]~combout add:inst|back[4]~84 add:inst|back[5]~85 add:inst|back[6]~86 add:inst|back[7]~87 add:inst|back[8]~88 add:inst|back[9]~89 add:inst|back[10]~90 add:inst|back[11]~91 add:inst|back[12]~92 add:inst|back[13]~93 add:inst|back[14]~94 add:inst|back[15]~71 add:inst|back[15] } { 0.000ns 0.000ns 6.405ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.935ns 0.621ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.773 ns" { clk clk~clkctrl add:inst|back[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.773 ns" { clk clk~combout clk~clkctrl add:inst|back[15] } { 0.000ns 0.000ns 0.139ns 0.878ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out\[3\] rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[3\] 8.576 ns memory " "Info: tco from clock \"clk\" to destination pin \"out\[3\]\" through memory \"rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[3\]\" is 8.576 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.848 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.804 ns) + CELL(0.815 ns) 2.848 ns rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[3\] 3 MEM M4K_X27_Y9 1 " "Info: 3: + IC(0.804 ns) + CELL(0.815 ns) = 2.848 ns; Loc. = M4K_X27_Y9; Fanout = 1; MEM Node = 'rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.619 ns" { clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 66.89 % ) " "Info: Total cell delay = 1.905 ns ( 66.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.943 ns ( 33.11 % ) " "Info: Total interconnect delay = 0.943 ns ( 33.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.848 ns" { clk clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.848 ns" { clk clk~combout clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.468 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[3\] 1 MEM M4K_X27_Y9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X27_Y9; Fanout = 1; MEM Node = 'rom01:inst1\|altsyncram:altsyncram_component\|altsyncram_t431:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_t431.tdf" "" { Text "E:/test/dds/db/altsyncram_t431.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.133 ns) + CELL(3.226 ns) 5.468 ns out\[3\] 2 PIN PIN_120 0 " "Info: 2: + IC(2.133 ns) + CELL(3.226 ns) = 5.468 ns; Loc. = PIN_120; Fanout = 0; PIN Node = 'out\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.359 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] out[3] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 336 824 1000 352 "out\[9..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.335 ns ( 60.99 % ) " "Info: Total cell delay = 3.335 ns ( 60.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.133 ns ( 39.01 % ) " "Info: Total interconnect delay = 2.133 ns ( 39.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.468 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] out[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.468 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] out[3] } { 0.000ns 2.133ns } { 0.109ns 3.226ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.848 ns" { clk clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.848 ns" { clk clk~combout clk~clkctrl rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.815ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.468 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] out[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.468 ns" { rom01:inst1|altsyncram:altsyncram_component|altsyncram_t431:auto_generated|q_a[3] out[3] } { 0.000ns 2.133ns } { 0.109ns 3.226ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "add:inst\|back\[0\] m\[0\] clk -0.187 ns register " "Info: th for register \"add:inst\|back\[0\]\" (data pin = \"m\[0\]\", clock pin = \"clk\") is -0.187 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.773 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.773 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 42 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 42; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 448 232 400 464 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.878 ns) + CELL(0.666 ns) 2.773 ns add:inst\|back\[0\] 3 REG LCFF_X29_Y9_N1 2 " "Info: 3: + IC(0.878 ns) + CELL(0.666 ns) = 2.773 ns; Loc. = LCFF_X29_Y9_N1; Fanout = 2; REG Node = 'add:inst\|back\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.544 ns" { clk~clkctrl add:inst|back[0] } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.32 % ) " "Info: Total cell delay = 1.756 ns ( 63.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.017 ns ( 36.68 % ) " "Info: Total interconnect delay = 1.017 ns ( 36.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.773 ns" { clk clk~clkctrl add:inst|back[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.773 ns" { clk clk~combout clk~clkctrl add:inst|back[0] } { 0.000ns 0.000ns 0.139ns 0.878ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.266 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.266 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns m\[0\] 1 PIN PIN_90 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_90; Fanout = 2; PIN Node = 'm\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { m[0] } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/test/dds/dds.bdf" { { 344 232 400 360 "m\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.408 ns) + CELL(0.650 ns) 3.158 ns add:inst\|back\[0\]~79 2 COMB LCCOMB_X29_Y9_N0 1 " "Info: 2: + IC(1.408 ns) + CELL(0.650 ns) = 3.158 ns; Loc. = LCCOMB_X29_Y9_N0; Fanout = 1; COMB Node = 'add:inst\|back\[0\]~79'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.058 ns" { m[0] add:inst|back[0]~79 } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.266 ns add:inst\|back\[0\] 3 REG LCFF_X29_Y9_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.266 ns; Loc. = LCFF_X29_Y9_N1; Fanout = 2; REG Node = 'add:inst\|back\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { add:inst|back[0]~79 add:inst|back[0] } "NODE_NAME" } } { "add.vhd" "" { Text "E:/test/dds/add.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.858 ns ( 56.89 % ) " "Info: Total cell delay = 1.858 ns ( 56.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.408 ns ( 43.11 % ) " "Info: Total interconnect delay = 1.408 ns ( 43.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.266 ns" { m[0] add:inst|back[0]~79 add:inst|back[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.266 ns" { m[0] m[0]~combout add:inst|back[0]~79 add:inst|back[0] } { 0.000ns 0.000ns 1.408ns 0.000ns } { 0.000ns 1.100ns 0.650ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.773 ns" { clk clk~clkctrl add:inst|back[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.773 ns" { clk clk~combout clk~clkctrl add:inst|back[0] } { 0.000ns 0.000ns 0.139ns 0.878ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.266 ns" { m[0] add:inst|back[0]~79 add:inst|back[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.266 ns" { m[0] m[0]~combout add:inst|back[0]~79 add:inst|back[0] } { 0.000ns 0.000ns 1.408ns 0.000ns } { 0.000ns 1.100ns 0.650ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -