dds.fit.eqn

这是一个用vhdl语言实现dds的例子

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--E1_q_a[7] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[7] at M4K_X17_Y7
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !GLOBAL(clk);
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out_reg[0];

--E1_q_a[0] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[0] at M4K_X17_Y7
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !GLOBAL(clk);
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[0] = E1_q_a[7]_PORT_A_data_out_reg[7];

--E1_q_a[1] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[1] at M4K_X17_Y7
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !GLOBAL(clk);
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[1] = E1_q_a[7]_PORT_A_data_out_reg[6];

--E1_q_a[2] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[2] at M4K_X17_Y7
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !GLOBAL(clk);
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[2] = E1_q_a[7]_PORT_A_data_out_reg[5];

--E1_q_a[3] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[3] at M4K_X17_Y7
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !GLOBAL(clk);
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[3] = E1_q_a[7]_PORT_A_data_out_reg[4];

--E1_q_a[4] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[4] at M4K_X17_Y7
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !GLOBAL(clk);
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[4] = E1_q_a[7]_PORT_A_data_out_reg[3];

--E1_q_a[5] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[5] at M4K_X17_Y7
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !GLOBAL(clk);
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[5] = E1_q_a[7]_PORT_A_data_out_reg[2];

--E1_q_a[6] is rom01:inst1|altsyncram:altsyncram_component|altsyncram_ipr:auto_generated|q_a[6] at M4K_X17_Y7
E1_q_a[7]_PORT_A_address = BUS(B1_adda[0], B1_adda[1], B1_adda[2], B1_adda[3], B1_adda[4], B1_adda[5], B1_adda[6], B1_adda[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = !GLOBAL(clk);
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7]_PORT_A_data_out_reg = DFFE(E1_q_a[7]_PORT_A_data_out, E1_q_a[7]_clock_0, , , );
E1_q_a[6] = E1_q_a[7]_PORT_A_data_out_reg[1];


--B1_adda[0] is add:inst|adda[0] at LC_X16_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_adda[0]_lut_out = GND;
B1_adda[0] = DFFEAS(B1_adda[0]_lut_out, GLOBAL(clk), VCC, , , B1_back[8], , , VCC);


--B1_adda[1] is add:inst|adda[1] at LC_X16_Y7_N9
--operation mode is normal

B1_adda[1]_lut_out = B1_back[9];
B1_adda[1] = DFFEAS(B1_adda[1]_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_adda[2] is add:inst|adda[2] at LC_X14_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_adda[2]_lut_out = GND;
B1_adda[2] = DFFEAS(B1_adda[2]_lut_out, GLOBAL(clk), VCC, , , B1_back[10], , , VCC);


--B1_adda[3] is add:inst|adda[3] at LC_X16_Y5_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_adda[3]_lut_out = GND;
B1_adda[3] = DFFEAS(B1_adda[3]_lut_out, GLOBAL(clk), VCC, , , B1_back[11], , , VCC);


--B1_adda[4] is add:inst|adda[4] at LC_X15_Y7_N2
--operation mode is normal

B1_adda[4]_lut_out = B1_back[12];
B1_adda[4] = DFFEAS(B1_adda[4]_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_adda[5] is add:inst|adda[5] at LC_X16_Y6_N2
--operation mode is normal

B1_adda[5]_lut_out = B1_back[13];
B1_adda[5] = DFFEAS(B1_adda[5]_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_adda[6] is add:inst|adda[6] at LC_X19_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_adda[6]_lut_out = GND;
B1_adda[6] = DFFEAS(B1_adda[6]_lut_out, GLOBAL(clk), VCC, , , B1_back[14], , , VCC);


--B1_adda[7] is add:inst|adda[7] at LC_X16_Y7_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_adda[7]_lut_out = GND;
B1_adda[7] = DFFEAS(B1_adda[7]_lut_out, GLOBAL(clk), VCC, , , B1_back[15], , , VCC);


--B1_back[8] is add:inst|back[8] at LC_X16_Y7_N0
--operation mode is arithmetic

B1_back[8]_carry_eqn = B1L32;
B1_back[8]_lut_out = B1_back[8] $ !B1_back[8]_carry_eqn;
B1_back[8] = DFFEAS(B1_back[8]_lut_out, GLOBAL(clk), VCC, , , , , , );

--B1L34 is add:inst|back[8]~113 at LC_X16_Y7_N0
--operation mode is arithmetic

B1L34_cout_0 = B1_back[8] & !B1L32;
B1L34 = CARRY(B1L34_cout_0);

--B1L35 is add:inst|back[8]~113COUT1_183 at LC_X16_Y7_N0
--operation mode is arithmetic

B1L35_cout_1 = B1_back[8] & !B1L32;
B1L35 = CARRY(B1L35_cout_1);


--B1_back[9] is add:inst|back[9] at LC_X16_Y7_N1
--operation mode is arithmetic

B1_back[9]_carry_eqn = (!B1L32 & B1L34) # (B1L32 & B1L35);
B1_back[9]_lut_out = B1_back[9] $ (B1_back[9]_carry_eqn);
B1_back[9] = DFFEAS(B1_back[9]_lut_out, GLOBAL(clk), VCC, , , , , , );

--B1L37 is add:inst|back[9]~117 at LC_X16_Y7_N1
--operation mode is arithmetic

B1L37_cout_0 = !B1L34 # !B1_back[9];
B1L37 = CARRY(B1L37_cout_0);

--B1L38 is add:inst|back[9]~117COUT1_184 at LC_X16_Y7_N1
--operation mode is arithmetic

B1L38_cout_1 = !B1L35 # !B1_back[9];
B1L38 = CARRY(B1L38_cout_1);


--B1_back[10] is add:inst|back[10] at LC_X16_Y7_N2
--operation mode is arithmetic

B1_back[10]_carry_eqn = (!B1L32 & B1L37) # (B1L32 & B1L38);
B1_back[10]_lut_out = B1_back[10] $ (!B1_back[10]_carry_eqn);
B1_back[10] = DFFEAS(B1_back[10]_lut_out, GLOBAL(clk), VCC, , , , , , );

--B1L40 is add:inst|back[10]~121 at LC_X16_Y7_N2
--operation mode is arithmetic

B1L40_cout_0 = B1_back[10] & (!B1L37);
B1L40 = CARRY(B1L40_cout_0);

--B1L41 is add:inst|back[10]~121COUT1_185 at LC_X16_Y7_N2
--operation mode is arithmetic

B1L41_cout_1 = B1_back[10] & (!B1L38);
B1L41 = CARRY(B1L41_cout_1);


--B1_back[11] is add:inst|back[11] at LC_X16_Y7_N3
--operation mode is arithmetic

B1_back[11]_carry_eqn = (!B1L32 & B1L40) # (B1L32 & B1L41);
B1_back[11]_lut_out = B1_back[11] $ B1_back[11]_carry_eqn;
B1_back[11] = DFFEAS(B1_back[11]_lut_out, GLOBAL(clk), VCC, , , , , , );

--B1L43 is add:inst|back[11]~125 at LC_X16_Y7_N3
--operation mode is arithmetic

B1L43_cout_0 = !B1L40 # !B1_back[11];
B1L43 = CARRY(B1L43_cout_0);

--B1L44 is add:inst|back[11]~125COUT1_186 at LC_X16_Y7_N3
--operation mode is arithmetic

B1L44_cout_1 = !B1L41 # !B1_back[11];
B1L44 = CARRY(B1L44_cout_1);


--B1_back[12] is add:inst|back[12] at LC_X16_Y7_N4
--operation mode is arithmetic

B1_back[12]_carry_eqn = (!B1L32 & B1L43) # (B1L32 & B1L44);
B1_back[12]_lut_out = B1_back[12] $ !B1_back[12]_carry_eqn;
B1_back[12] = DFFEAS(B1_back[12]_lut_out, GLOBAL(clk), VCC, , , , , , );

--B1L46 is add:inst|back[12]~129 at LC_X16_Y7_N4
--operation mode is arithmetic

B1L46 = CARRY(B1_back[12] & !B1L44);


--B1_back[13] is add:inst|back[13] at LC_X16_Y7_N5
--operation mode is arithmetic

B1_back[13]_carry_eqn = B1L46;
B1_back[13]_lut_out = B1_back[13] $ B1_back[13]_carry_eqn;
B1_back[13] = DFFEAS(B1_back[13]_lut_out, GLOBAL(clk), VCC, , , , , , );

--B1L48 is add:inst|back[13]~133 at LC_X16_Y7_N5
--operation mode is arithmetic

B1L48_cout_0 = !B1L46 # !B1_back[13];
B1L48 = CARRY(B1L48_cout_0);

--B1L49 is add:inst|back[13]~133COUT1_187 at LC_X16_Y7_N5
--operation mode is arithmetic

B1L49_cout_1 = !B1L46 # !B1_back[13];
B1L49 = CARRY(B1L49_cout_1);


--B1_back[14] is add:inst|back[14] at LC_X16_Y7_N6
--operation mode is arithmetic

B1_back[14]_carry_eqn = (!B1L46 & B1L48) # (B1L46 & B1L49);
B1_back[14]_lut_out = B1_back[14] $ (!B1_back[14]_carry_eqn);
B1_back[14] = DFFEAS(B1_back[14]_lut_out, GLOBAL(clk), VCC, , , , , , );

--B1L51 is add:inst|back[14]~137 at LC_X16_Y7_N6
--operation mode is arithmetic