dds.fit.summary

这是一个用vhdl语言实现dds的例子

Fitter Status : Successful - Thu Dec 27 09:14:46 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone II
Device : EP2C8T144C8
Timing Models : Final
Total logic elements : 24 / 8,256 ( < 1 % )
Total registers : 24
Total pins : 19 / 85 ( 22 % )
Total virtual pins : 0
Total memory bits : 2,560 / 165,888 ( 2 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )