reset.s

MIPS下的boottloader yamon 的源代码

/************************************************************************
 *
 *  reset.S
 *
 *  Startup code for bootprom
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
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 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
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 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
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 *
 ************************************************************************/

/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <mips.h>
#include <shell_api.h>
#include <sys_api.h>
#include <pb1000.h>
			
/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

/************************************************************************
 *
 *                          __reset_handler
 *  Description :
 *  -------------
 *
 *  Exception handler entry points for bootprom.
 *  including reset vector (0xbfc00000).
 *
 *  Return values :
 *  ---------------
 *
 *  For interrupts, function simply returns
 *  For exceptions, function never returns
 *
 *  In case of the reset exception, function jumps to the start function,
 *  which after doing various initialisation, jumps to the first C-function (main).
 *  main() is not supposed to return. If it does so anyway, start() displays
 *  an error message (depending on platform) and enters an infinite loop
 *
 ************************************************************************/
LEAF(__reset_handler)

//#define BOOT_16BIT
//#define DUAL_BOOT_16BIT

/*
 * Setup ability to have both big and little endian YAMON
 * contained within a 16-bit boot device.
 */
#ifdef DUAL_BOOT_16BIT
#if defined(EB) || !defined(EL)
#error "Must compile this reset code little endian!!!"
#endif
#if defined(BOOT_16BIT)
#error "Can only declare one of DUAL_BOOT_16BIT or BOOT_16BIT"
#endif
#define BOOT_16BIT
#endif

	.set noreorder
#ifdef BOOT_16BIT
#ifdef EL
	/*
	 * When the Au1 core is to run little-endian, there is nothing
	 * special to do here since the static memory controller defaults
	 * to a little-endian ordering. And though the core defaults to
	 * big-endian mode, the static memory controller properly
	 * reads 32-bit values (i.e. instructions) from the little-endian
	 * ordered 16-bit wide memory. However, the core must change to
	 * little-endian before any data accesses occur, else the 8- or
	 * 16-bit data will be incorrect (32-bit data is still correct).
	 */
#endif

#ifdef EB
	/*
	 * When the Au1 core is to run big-endian, the endian mode of
	 * the static memory controller must be changed to big-endian.
	 * The static memory controller defaults to little-endian
	 * ordering out of reset, so boot code compiled big-endian
	 * must be half-word swapped until the mem_stcfg0[BE] is set.
	 * The .long values below are the halfword-swapped values of
	 * the resulting instructions in the comments to the right which
	 * properly set mem_stcfg0[BE]=1.
	 */
	.long 0xb4003c08 # lui     t0,0xb400
	.long 0x10003508 # ori     t0,t0,0x1000
	.long 0x00008d09 # lw      t1,0(t0)
	.long 0x02003529 # ori     t1,t1,0x200
	.long 0x0000ad09 # sw      t1,0(t0)
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
#endif
#endif /* BOOT_16BIT */

	/**** linked cached (start address 0x9fc00000)
	 **** Processor is running code uncached (i.e. 0xbfc00000)
	 ****/
	
	
	/*  Address 0xBfc00010 is reserved for boardID, so
	 *  branch to 0xBfc00018 (registers on CBUS are 64
	 *  bit aligned).
	 */
	b	reset_au1xxx      /* 0xBfc00000 */
	nop		/* 0xBfc00004 */
	nop		/* 0xBfc00008 */
	nop		/* 0xBfc0000C */
	
.org 0x80 /* MIPS_REVISION */
	/* Revise: - This is the board ID */
	/* bits 32:24 - res - 0
	   bits 23:16 - FPGRV - 0 (N/A)
	   bits 15:10 - CORID - 0x2
	   bits 9:8 - CORRV - 0
	   bits 7:4 - PROID - 0x4
	   bits 3:0 - PRORV - 0x0 ??? */
	/*.long 0x00000840 */
	/*.long 0x08400000 */ /* halfword-swapped version */

	nop

digit:	/* Used for determining endianness */
	.word 0x12345678

	
.org 0x400
	/* 0xBFC00400 Catch other exceptions, except EJTAG debug */

	/* Check for interrupt */
	MFC0(   k0, C0_CAUSE )
	and	k0, C0_CAUSE_CODE_MSK
	srl	k0, C0_CAUSE_CODE_SHF
	subu	k0, C0_CAUSE_CODE_INT
	beq	k0, zero, interrupt
	nop
	/* Not an interrupt */
1:	
	b	1b
	nop	

interrupt:		
	/* Interrupt : For now we simply disable interrupts and return */
	
	MFC0(   k0, C0_STATUS)
	srl	k0, 1
	sll	k0, 1		
	MTC0(	k0, C0_STATUS)
	.set mips3
	eret
	.set mips2

.org 0x480
       /* 0xBFC00480 EJTAG debug exception */
       li       k0, KSEG0(SYS_EJTAG_RAM_VECTOR_OFS)
       jr	k0
       nop

.org 0x500
       /* 0xBFC00500 Vector table for shell functions */

#define ILLEGAL 0xffffffff

       .word    ILLEGAL
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_PRINT_COUNT_CODE * 8
       .word	ILLEGAL
       .word	ILLEGAL
       .word	ILLEGAL
       .word	ILLEGAL
       .word	ILLEGAL
       .word	ILLEGAL
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_EXIT_CODE * 8
       .word	ILLEGAL
       .word	ILLEGAL
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_FLUSH_CODE * 8
       .word	ILLEGAL
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_PRINT_CODE * 8
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_REGISTER_CPU_ISR_CODE * 8
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_DEREGISTER_CPU_ISR_CODE * 8
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_REGISTER_IC_ISR_CODE * 8
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_DEREGISTER_IC_ISR_CODE * 8
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_REGISTER_ESR_CODE * 8
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_DEREGISTER_ESR_CODE * 8
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_GETCHAR_CODE * 8 
       .word	SHELL_VECTOR_ADDR + SHELL_FUNC_SYSCON_READ_CODE * 8
	
END(__reset_handler)


	/*
	 * Perform Au1XXX reset configuration
	 */
reset_au1xxx:
	nop
	nop

#ifdef PB1000_CONFIG
#include "../arch/init/reset_pb1000.S"
#endif

#ifdef PB1500_CONFIG
#include "../arch/init/reset_pb1500.S"
#endif

#ifdef PB1100_CONFIG
#include "../arch/init/reset_pb1100.S"
#endif

#ifdef PB1550_CONFIG
#include "../arch/init/reset_pb1550.S"
#endif
	
#ifdef PB1200_CONFIG
#include "../arch/init/reset_pb1200.S"
#endif

#ifdef DB1000_CONFIG
#include "../arch/init/reset_db1000.S"
#endif

#ifdef DB1500_CONFIG
#include "../arch/init/reset_db1500.S"
#endif

#ifdef DB1100_CONFIG
#include "../arch/init/reset_db1100.S"
#endif

#ifdef DB1550_CONFIG
#include "../arch/init/reset_db1550.S"
#endif

#ifdef DB1200_CONFIG
#include "../arch/init/reset_db1200.S"
#endif

#ifdef HYDROGEN_CONFIG
#include "../arch/init/reset_hydrogen.S"
#endif

#ifdef HYD1100_CONFIG
#include "../arch/init/reset_hydrogen.S"
#endif

#ifdef H3_CONFIG
#include "../arch/init/reset_hydrogen3.S"
#endif

#ifdef BE1000_CONFIG
#include "../arch/init/reset_be1000.S"
#endif

#ifdef BOSPORUS_CONFIG
#include "../arch/init/reset_bosporus.S"
#endif

#ifdef TI1500_CONFIG
#include "../arch/init/reset_ti1500.S"
#endif

#ifdef MIRAGE_CONFIG
#include "../arch/init/reset_mirage.S"
#endif

#ifdef WIDGET_CONFIG
#include "../arch/init/reset_widget.S"
#endif

#ifdef SDV2_CONFIG
#include "../arch/init/reset_sdv2.S"
#endif

#ifdef 	FICMMP_CONFIG
#include "../arch/init/reset_ficmmp.S"
#endif

	/*
	 * Examine Config0[BE] to determine little or big endian YAMON
	 */
	MFC0(   k0, C0_CONFIG)
	and	k0,k0,0x8000
	beq	zero, k0, yamon_le

	la	k0, _reset_handler_be   /* Defined in linker script */
	KSEG1A( k0 )			/* Make sure it is uncached */

#ifndef DUAL_BOOT_16BIT
	j	k0
	nop

#else
	/*
	 * Set mem_stcfg0[BE]=1, and must manually swap the next
	 * instructions which jump to the big endian image. There
	 * are 8 NOPs to ensure that the swapped instructions are
	 * not cached (with the non-swapped instructions before
	 * the change to mem_stcfg[BE] takes place).
	 */
	li		t0, 0xB4001000	# load addr of mem_stcfg0
	lw		t1, 0(t0)		# read value of mem_stcfg0
	ori		t1, t1, 0x0200  # mem_stcfg[BE]=1
	sw		t1, 0(t0)		# write value to mem_stcfg0
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00080340 # jr k0
	.long 0x00000000 # nop
	.long 0x00000000 # nop
	.long 0x00000000 # nop
#endif


yamon_le:

	la	k0, _reset_handler_le   /* Defined in linker script */
	KSEG1A( k0 )			/* Make sure it is uncached */
	j	k0
	nop


/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/