main.c

MIPS下的boottloader yamon 的源代码

/************************************************************************
 *
 *  main.c
 *
 *  First C-function
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <syscon_api.h>
#include <sys_api.h>
#include <initmodules_api.h>
#include <env_api.h>
#include <shell_api.h>
#include <loader_api.h>
#include <init.h>
#include <product.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

/*  Macro for conversion between time interval in ns and number of
 *  SysAD bus cycles.
 *  Round result down.
 */
#define NS2COUNT_ROUND_DOWN(ns,count)	\
    count =  sys_busfreq_hz / 1000000;  \
    count *= ns;			\
    count /= 1000;

/*  Macro for conversion between time interval in ns and number of
 *  SysAD bus cycles.
 *  Round result up.
 */
#define NS2COUNT_ROUND_UP(ns,count)		   \
    count =  (sys_busfreq_hz + 999999) / 1000000;  \
    count *= ns;				   \
    count =  (count + 999) / 1000;

/************************************************************************
 *  Public variables (some not used here)
 ************************************************************************/

UINT32 sys_processor;
UINT32 sys_platform;
UINT32 sys_corecard;
UINT32 sys_nb_base;
UINT32 sys_ramsize;
UINT32 sys_freemem;
bool   sys_64bit;

UINT32 sys_icache_linesize;
UINT32 sys_icache_lines;
UINT32 sys_icache_assoc;
UINT32 sys_dcache_linesize;
UINT32 sys_dcache_lines;
UINT32 sys_dcache_assoc;

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Static function prototypes
 ************************************************************************/

static void
core_optimize( void );

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

/************************************************************************
 *
 *                          c_entry
 *  Description :
 *  -------------
 *
 *  First C-function
 *
 *  Return values :
 *  ---------------
 *
 *  Never returns
 *
 ************************************************************************/
int
c_entry(void)
{
    t_sys_cpu_decoded decoded;
    bool	      init_from_env;

    /* Determine whether we have a 32 or 64 bit CPU */
    sys_64bit = sys_cpu_type() ? TRUE : FALSE;

    /*  Early (before module initialisation)
     *  platform specific initialisation 
     */
   
	arch_platform_init( TRUE );
      
    /* Initialise modules (defined in initmodules.h and initswitch.h) */

	
    initmodules();
  
    /* Optimise system controller settings */

	/* Core optimize messes with SDRAM settings.  Ours will be OK from the start 
	   Write functions that core_optimize calls are not implemented */
#if 0
	if(sys_platform != PRODUCT_PB1000_ID)
    core_optimize();
#endif

    /*  Late (after module initialisation)
     *  platform specific initialisation 
     */
    arch_platform_init( FALSE );

    /* Configure cpu according to environment variable "cpuconfig" */

    /*  This feature is present specifically to support configuration
     *  testing of the core in a lead vehicle, and is not supported
     *  in any other environment.  Attempting to use this feature
     *  outside of the scope of a lead vehicle is a violation of the
     *  MIPS Architecture, and may cause unpredictable operation of
     *  the processor.
     */
#if 0
    SYSCON_read( SYSCON_BOARD_INIT_BASED_ON_ENV_ID,
		 (void *)&init_from_env, sizeof(bool) );

    if( init_from_env &&
        env_get( "cpuconfig", NULL, &decoded, sizeof(t_sys_cpu_decoded) ) )
    {
        DISP_STR( "CPU_U" );
	sys_cpu_config( TRUE, TRUE, TRUE, &decoded );
    }
#endif

    DISP_STR("INITDONE");

    /* Initialise loader (TBD : load could be handled as any other module) */
    loader_init();

    /* Done with initialisation. Now jump to shell (never returns) */
    shell_setup();

    return ERROR_STRUCTURE;	/* Should never happen */
}


/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/


/************************************************************************
 *
 *                          core_optimize
 *  Description :
 *  -------------
 *
 *  Re-configure system controller based on detected bus frequency.
 *
 *  Read various SDRAM requirements in ns, convert to number 
 *  of cycles at the SysAD bus frequency and configure using 
 *  this number.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
#if 0
static void
core_optimize()
{
    UINT32 ns, count;

    /* count = bus frequency (in MHz) * rate (in us) */

    /**** Refresh rate ****/

    /* Read rate */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_REFRESH_NS_ID,
		    &ns, sizeof(UINT32)) == OK)
    {
        NS2COUNT_ROUND_DOWN(ns,count);

	/* Write cycles */
        SYSCON_write( SYSCON_BOARD_SYSTEMRAM_REFRESH_CYCLES_ID,
		      &count, sizeof(UINT32) );
    }

    /**** SRAS precharge time ****/

    /* Read rate */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_SRASPRCHG_NS_ID,
		    &ns, sizeof(UINT32)) == OK)
    {
        NS2COUNT_ROUND_UP(ns,count);

	/* Write cycles */
        SYSCON_write( SYSCON_BOARD_SYSTEMRAM_SRASPRCHG_CYCLES_ID,
		      &count, sizeof(UINT32) );
    }

    /**** SRAS to SCAS delay ****/

    /* Read rate */
    if(SYSCON_read( SYSCON_BOARD_SYSTEMRAM_SRAS2SCAS_NS_ID,
		    &ns, sizeof(UINT32)) == OK)
    {
        NS2COUNT_ROUND_UP(ns,count);

	/* Write cycles */
        SYSCON_write( SYSCON_BOARD_SYSTEMRAM_SRAS2SCAS_CYCLES_ID,
		      &count, sizeof(UINT32) );
    }
}

#endif