init.s

MIPS下的boottloader yamon 的源代码

	li	v0, ERROR_SPD

	/* bank 0 */
	li	BSIZE0, 512*1024*1024
1:	
	and	t0, v1, 1 << 7
	bne	t0, zero, 2f
	sll	v1, 1
	b	1b
	srl	BSIZE0, 1
2:
	/* bank 1 (if available) */
	li	t0, 1
	beq	MOD_BANKS, t0, 2f		/* 1 bank only		*/
	move	BSIZE1, zero
	and	v1, 0xFF
	beq	v1, zero, 2f
	move	BSIZE1, BSIZE0			/* 2 symmetrical banks	*/

	/*  2 asymmetrical banks. We assume that bank0 is largest.
	 *  (TBD : Is this a fair assumption ?)
	 */
1:
	srl	BSIZE1, 1
	and	t0, v1, 1 << 7
	beq	t0, zero, 1b
	sll	v1, 1
2:

#undef MOD_BANKS

        /* s0..s6 used */

	/*  Validate SDRAM parameters.
	 *
	 *  The following data is available :
	 *
	 *  RAMSIZE_MAX = Max allowed RAM size.
	 *  BSIZE0      = size(bank0) (in bytes).
	 *  BSIZE1      = size(bank1) (in bytes) (if available).
	 *
	 *  Checks performed :	
	 *
	 *  BSIZE<n>          <= BANKSIZE_MAX
	 *  Total memory size <= RAMSIZE_MAX
	 */

	/*  Check and possibly adjust bank0 size :
         *  BSIZE0 <= MIN(BANKSIZE_MAX, RAMSIZE_MAX)
         */

	/* Calc t0 = MIN(BANKSIZE_MAX, RAMSIZE_MAX) */
	sltu    t0, BANKSIZE_MAX, RAMSIZE_MAX
	bne	t0, zero, 1f
	move	t0, BANKSIZE_MAX /* Branch delay slot */
	move	t0, RAMSIZE_MAX
1:
	/* Perform check on BSIZE0 */
	sltu	t1, t0, BSIZE0
	beq	t1, zero, 1f
	nop
	/* bank 0 too large, so adjust size */
	move	BSIZE0, t0
1:

	/*  Check and possibly adjust bank1 size.
	 *  BSIZE1 <= MIN(BANKSIZE_MAX, RAMSIZE_MAX - BSIZE0)
         */

	/* Calc t0 = MIN(BANKSIZE_MAX, RAMSIZE_MAX - BSIZE0) */
	subu    t1, RAMSIZE_MAX, BSIZE0    
	sltu	t0, BANKSIZE_MAX, t1
	bne	t0, zero, 1f
	move	t0, BANKSIZE_MAX /* Branch delay slot */
	move	t0, t1
1:
	/* Perform check on BSIZE1 */
	sltu	t1, t0, BSIZE1
	beq	t1, zero, done
	nop
	/* bank 1 too large, so adjust size */
	move	BSIZE1, t0

done:
	/* Setup return parameters */
	move	 v0, zero
	move	 v1, DEV_SIZE
	move	 t0, DEV_BANKS
	move	 t1, BSIZE0
	move	 t2, BSIZE1

error_sdram:
	jr	RA
	nop

#undef RA
#undef RAMSIZE_MAX
#undef BANKSIZE_MAX
#undef DEV_BANKS
#undef DEV_SIZE
#undef BSIZE0
#undef BSIZE1
	
END(sys_determine_sdram_parms)
	

/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/
	
/************************************************************************
 *  sys_memory_setup
 ************************************************************************/
LEAF(sys_memory_setup)

	/*  a0 = RAM size */

	/* First calc start, middle and end addresses	*/
	li	t0, KSEG1(0)	/* First	   	*/
	add	t2, t0, a0	/* First non valid 	*/
	move	t1, t0
	srl	t6, a0, 1
	add	t1, t6		/* Middle+4		*/

	/*  Test first, middle and last address by writing magic values and
	 *  reading values back. The middle value is needed to test for
	 *  mirroring.
	 */

	DISP_STR( msg_ramtest_hilo )
 
	/* Setup values */
#define MAGIC_LO	0xAAAAAAAA
#define MAGIC_MI	0xFedeBabe
#define MAGIC_HI	0x55555555

	li	t3, MAGIC_LO
	li	t4, MAGIC_MI
	li	t5, MAGIC_HI

	/* Perform the writes */
	sw	t3,  0(t0)	/* first */

	move	t1, t0
	srl	t6, a0, 1
	add	t1, t6	
	sw	t4, -4(t1)	/* (last/2)-4 */

	move	t1, t0
	srl	t6, a0, 2
	add	t1, t6	
	sw	t4, -4(t1)	/* (last/4)-4 */

	move	t1, t0
	srl	t6, a0, 3
	add	t1, t6	
	sw	t4, -4(t1)	/* (last/8)-4 */

	move	t1, t0
	srl	t6, a0, 1
	add	t1, t6	
	srl	t6, a0, 2
	add	t1, t6	
	sw	t4, -4(t1)	/* (last/2) + (last/4) - 4 */

	move	t1, t0
	srl	t6, a0, 1
	add	t1, t6	
	srl	t6, a0, 2
	add	t1, t6	
	srl	t6, a0, 3
	add	t1, t6	
	sw	t4, -4(t1)	/* (last/2) + (last/4) + (last/8) - 4 */

	sw	t5, -4(t2)	/* last-4 */



	/* Perform the reads and compares */
	lw	v0,  0(t0)
	bne	v0, t3, error
	li	v0, ERROR_RAM_LO

	move	t1, t0
	srl	t6, a0, 1
	add	t1, t6	
	lw	v0, -4(t1)	/* (last/2) - 4 */
	bne	v0, t4, error
	li	v0, ERROR_RAM_MI



	move	t1, t0
	srl	t6, a0, 2
	add	t1, t6	
	lw	v0, -4(t1)	/* (last/4) - 4 */
	bne	v0, t4, error
	li	v0, ERROR_RAM_MI

	move	t1, t0
	srl	t6, a0, 3
	add	t1, t6	
	lw	v0, -4(t1)	/* (last/8) - 4 */
	bne	v0, t4, error
	li	v0, ERROR_RAM_MI

	move	t1, t0
	srl	t6, a0, 1
	add	t1, t6	
	srl	t6, a0, 2
	add	t1, t6	
	lw	v0, -4(t1)	/* (last/2) + (last/4) - 4 */
	bne	v0, t4, error
	li	v0, ERROR_RAM_MI

	move	t1, t0
	srl	t6, a0, 1
	add	t1, t6	
	srl	t6, a0, 2
	add	t1, t6	
	srl	t6, a0, 3
	add	t1, t6	
	lw	v0, -4(t1)	/* (last/2) + (last/4) + (last/8) - 4 */
	bne	v0, t4, error
	li	v0, ERROR_RAM_MI


	lw	v0, -4(t2)
	bne	v0, t5, error
	li	v0, ERROR_RAM_HI

	/* ok */
	move	v0, zero
	

	/* Perform test of yamon RAM */

	DISP_STR( msg_ramtest_yamon )

	li	a0, KSEG1(0)	        /* start	*/
#ifdef _SIMULATE_
	li	a1, 0x0400		/* only test 1KByte */
#else


	la	a1, _freemem
	li	t0, SYS_STACK_SIZE
	addu	a1, t0 
	KUSEGA( a1 )			/* size		*/
#endif
	move    a2, zero		/* no callback  */
	move	s1, ra
	jal	sys_memory_test		
	nop
	move	ra, s1
	bne	v0, zero, error	
	nop
	move	v0, zero

	/* Perform memory clear */

mem_clear:	
	
	DISP_STR( msg_ram_clear )
	
	la     t0, _fbss
	la     t1, _end
	addiu  t1, -4
	KSEG0A(  t0 )
	KSEG0A(  t1 )
1:
	sw      zero,  0(t0)
	bne	t0, t1, 1b
	add	t0, 4

mem_setup_done :		
	jr	ra
	nop
		
END(sys_memory_setup)	


/************************************************************************
 *
 *                          sys_memory_test
 *  Description :
 *  -------------
 *
 *  Perform memory test
 *
 *  Parameters :
 *  ------------
 *
 *  a0 = RAM start address
 *  a1 = RAM size
 *  a2 = Callback function called at intervals
 *
 *  Callback function must preserve the state of t0..t4, a0..a2, v1
 *
 *  Return values :
 *  ---------------
 *
 *  0 If OK, error code != 1 if error
 *
 ************************************************************************/
LEAF(sys_memory_test)

#define ADDR     t0
#define LAST     t1
#define DATA     t2
#define RA       t3
#define MASK	 t4	
	
	move    RA, ra
	KSEG1A( a0 )
	
	/**** WORD ACCESSES ****/

	li	t4, 0xFFFFF

	/* Default error */
	li	v1, ERROR_MEMTEST_WORD
	
	addu	LAST, a0, a1
	addiu	LAST, -4

	/* Write */
	move	ADDR, a0
	move	DATA, zero
1:
	sw	DATA, 0(ADDR)
	and	t5, ADDR, t4
	bne	t5, zero, 2f
	addiu	DATA, 1
	/* time for callback */
	beq     a2, zero, 2f
	nop
	/* do callback */
	bal	do_callback
	nop
	bne	v0, zero, mem_test_done
	nop
2:
	bne	ADDR, LAST, 1b
	addiu	ADDR, 4

	/* Read */
	move	ADDR, a0
	move	DATA, zero
1:
	lw	t5, 0(ADDR)
	bne	t5, DATA, mem_test_done
	and	t5, ADDR, t4
	bne	t5, zero, 2f
	addiu	DATA, 1
	/* time for callback */
	beq	a2, zero, 2f
	nop
	/* do callback */
	bal	do_callback
	nop
	bne	v0, zero, mem_test_done
	nop
2:
	bne	ADDR, LAST, 1b
	addiu	ADDR, 4

	/**** BYTE ACCESSES ****/

	li	t4, 0x3FFFF

	/* Default error */
	li	v1, ERROR_MEMTEST_BYTE
	
	addu	LAST, a0, a1
	addiu	LAST, -1
	
	/* Write */
	move	ADDR, a0
	move	DATA, zero
1:
	sb	DATA, 0(ADDR)
	and	t5, ADDR, t4
	bne	t5, zero, 2f
	addiu	DATA, 1
	/* time for callback */
	beq	a2, zero, 2f
	nop
	/* do callback */
	bal	do_callback
	nop
	bne	v0, zero, mem_test_done
	nop
2:
	bne	ADDR, LAST, 1b
	addiu	ADDR, 1

	/* Read */
	move	ADDR, a0
	move	DATA, zero
1:
	lbu	t5, 0(ADDR)
	bne	t5, DATA, mem_test_done
	and	t5, ADDR, t4
	bne	t5, zero, 2f
	addiu	DATA, 1
	/* time for callback */
	beq	a2, zero, 2f
	nop
	/* do callback */
	bal	do_callback
	nop
	bne	v0, zero, mem_test_done
	nop
2:
	and	DATA, 0xFF
	bne	ADDR, LAST, 1b
	addiu	ADDR, 1
	
	/* No error */
	move	v1, zero
	
	/**** DONE ****/

mem_test_done:		
	jr	RA
	move	v0, v1



do_callback:	

     /* Store necessary context and call registered function */

     la	   t5, store_data
     sw    t0, 0x0(t5)
     sw    t1, 0x4(t5)
     sw    t2, 0x8(t5)
     sw    t3, 0xc(t5)
     sw    t4, 0x10(t5)
     sw    a0, 0x14(t5)
     sw    a1, 0x18(t5)
     sw    a2, 0x1c(t5)
     sw    v1, 0x20(t5)				
     sw	   ra, 0x24(t5)

     jalr  a2
     nop

     la	   t5, store_data
     lw    t0, 0x0(t5)
     lw    t1, 0x4(t5)
     lw    t2, 0x8(t5)
     lw    t3, 0xc(t5)
     lw    t4, 0x10(t5)
     lw    a0, 0x14(t5)
     lw    a1, 0x18(t5)
     lw    a2, 0x1c(t5)
     lw    v1, 0x20(t5)				
     lw	   ra, 0x24(t5)

     jr	   ra
     nop

	
END(sys_memory_test)


	
/******* Messages ********/

	.text

MSG( msg_cpu,	        "CPU" )
MSG( msg_platform,      "BOARD" )	
MSG( msg_ram,	        "RAM" )
MSG( msg_copy_code,     "COPYTEXT" )
MSG( msg_copy_data,     "COPYDATA" )		
MSG( msg_ramtest_hilo,  "RAM_HILO" )
MSG( msg_gothere,		"GOT HERE")
MSG( msg_ramtest_yamon, "RAM_TEST" )
MSG( msg_ram_clear,	"CLEAR" )
MSG( msg_sp,		"STACK" )
MSG( msg_info,		"INFO" )
MSG( msg_cache_info,    "CINFO" )
MSG( msg_main,		"FIRSTC" )

/* Error messages (see init.h) */
ERROR_MESSAGES