init.s

MIPS下的boottloader yamon 的源代码

/************************************************************************
 *
 *  init.S
 *
 *  Startup code for bootprom
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/

/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <mips.h>
#include <product.h>
#include <init.h>
#include <sys_api.h>
#include <spd.h>
#include <pb1000.h>
					
/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

	BSS

store_data:
	.space	10*4
		
/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

/*  Public address for returning from call to 
 *  sys_platform_early (see below) 
 */
.globl sys_platform_early_done
	
/************************************************************************
 *  reset_handler
 ************************************************************************/
LEAF(__reset_handler_end)

/* This is the entry point of the endian dependant code. It is called
 * from the reset handler (reset.S) located at bfc00000. Processor is running
 * at uncached addresses, but this code was linked cached. This function
 * will shift to cached when caches have been initialised.
 */	
	.set noreorder

	/* Setup cause register (clear cause code)  */
	li	k0, C0_CAUSE_IV_BIT
	MTC0(	k0, C0_CAUSE)

	/* Determine platform */
	li	k0, MIPS_REVISION

	li	k1, MIPS_REVISION_PROID_MSK
	and	k0, k1
	li	k1, MIPS_REVISION_PROID_SHF
	srlv	k0, k0, k1

	/**** k0 now holds the boardID field ****/

	/*  Early platform specific initialisation.
	 *  Also detects NMI.
	 *  Can't do jal since we don't want to modify ra register
	 *  in case an NMI has occurred.
	 *  Instead, sys_early_platform shall jump to
	 *  sys_platform_early_done when it is done.
	 */
	la	k1, sys_platform_early
	KSEG1A( k1 )  /* Make it uncached */
	jr	k1	
	nop

sys_platform_early_done:
	
	/*  From now on, we can use the display macro
	 *  (if platform supports it) 
	 */

	bne	v0, zero, error
	nop
	
	/* Determine processor */
	MFC0(   k1, C0_PRID)
	/*li	t0, C0_PRID_PRID_MSK | C0_PRID_COMP_MSK*/
	li		t0, 0x00FF0000
	and     k1, t0

	/**** k1 now holds the ProcessorID field ****/

	/* Perform CPU specific initialisation */

	DISP_STR( msg_cpu )
		
	la	t0, sys_init_processor
	KSEG1A( t0 )  /* Make it uncached */
	jalr	t0
	nop
1:
	bne	v0, zero, error
	nop

	/*  Initialise caches. If compiled for simulation, we
	 *  skip this since caches can be assumed to be invalidated.
	 */
	
#ifndef _SIMULATE_

	la	t0, sys_init_cache
	KSEG1A( t0 )  /* Make it uncached */
	jalr	t0
	nop
1:
	
	bne	v0, zero, error
	nop
	
#endif /* #ifndef _SIMULATE_ */
	
	/* Caches have now been initialised, so shift to kseg0 */
	la	t0, 1f
	KSEG0A( t0)
	j	t0
	nop
1:

	/**** From now on, we are executing cached ****/
	
	/* Determine platform */

	DISP_STR( msg_platform )
	
	/* 
	 * Perform platform specific initialisation.
	 *
	 * This does not include memory test/clear.
	 * The function returns the following parameters :
	 * v0 = error code (0 = no error)
	 * v1 = RAM size in bytes
	 */

	jal	sys_init_platform
	nop
1:
	bne	v0, zero, error
	nop
	
	move	s0, v1

	/**** s0 now holds RAM size in bytes ****/

	/* Now perform memory test/clear */

	DISP_STR( msg_ram )
	
	move	a0, s0
	jal	sys_memory_setup	/* v0 != 0 on error */
	nop
	bne	v0, zero, error
	nop

	/* Copy code to RAM */

	DISP_STR( msg_copy_code )
	
#ifndef _SIMULATE_
		
	la	t0, _etext_init		/* SRC  */
	la	t1, _ftext_ram		/* DST  */
	la	t2, _etext_ram		/* STOP */
	KSEG0A( t1 )
	KSEG0A( t2 )
	beq	t1, t2, copy_data
	nop
1:	
	lw	t3, 0(t0)
	add	t0, 4		
	sw	t3, 0(t1)
	
	/* Whenever an instruction has been stored to KSEG0, we must
	 * make sure the instruction has been flushed to physical memory
	 * and invalidate the corresponding I-Cache line.
	 */
	.set mips3
	cache   DCACHE_ADDR_HIT_WRITEBACK, 0(t1)	
	.set mips0
	sync
	ICACHE_ADDR_INVALIDATE_OP(t1,a0)
	
	bne	t1, t2, 1b
	add	t1, 4

#endif /* #ifndef _SIMULATE_ */

	/* Copy initialised data to RAM */
	
copy_data:		

	DISP_STR( msg_copy_data )
	
	la	t0, _etext		/* SRC  */
	la	t1, _fdata		/* DST  */
	la	t2, _fbss		/* STOP */
	KSEG0A( t1 )
	KSEG0A( t2 )
	beq	t1, t2, setup_sp
	nop
1:
	lw	t3, 0(t0)
	add	t0, 4
	sw	t3, 0(t1)
	bne	t1, t2, 1b
	add	t1, 4

setup_sp :

	/* Setup sp (at top of memory) */

	DISP_STR( msg_sp )
	
	la	 sp, _freemem
	li	 t0, SYS_STACK_SIZE
	addu	 sp, t0

	/* Setup gp */
	la	 gp, _gp

 	/* Store system info */

	DISP_STR( msg_info )
	
	la	t0, sys_processor
	sw	k1, 0(t0)
	la	t0, sys_platform
	sw	k0, 0(t0)
	la	t0, sys_ramsize
	sw	s0, 0(t0)
	
	/* Core card */
	li	t1, MIPS_REVISION
	li	t0, MIPS_REVISION_CORID_MSK
	and	t1, t0
	li	t0, MIPS_REVISION_CORID_SHF
	srlv	t1, t1, t0
	la	t0, sys_corecard
	sw	t1, 0(t0)
		
	/* Redetermine cache info and store it */

	DISP_STR( msg_cache_info )
	
	move	a0, k1

	jal	sys_determine_icache_assoc_flash
	nop
	la	t0, sys_icache_assoc
	sw	v0, 0(t0)
	
	jal	sys_determine_icache_lines_flash
	nop
	la	t0, sys_icache_lines
	sw	v0, 0(t0)

	jal	sys_determine_icache_linesize_flash
	nop
	la	t0, sys_icache_linesize
	sw	v0, 0(t0)

	jal	sys_determine_dcache_assoc_flash
	nop
	la	t0, sys_dcache_assoc
	sw	v0, 0(t0)
				
	jal	sys_determine_dcache_lines_flash
	nop
	la	t0, sys_dcache_lines
	sw	v0, 0(t0)
		
	jal	sys_determine_dcache_linesize_flash
	nop
	la	t0, sys_dcache_linesize
	sw	v0, 0(t0)

        /*  Calc first free RAM address. We add the dcache line size
	 *  to avoid cache writeback problem if user executes uncached
	 *  code.
	 */
	li	t0, SYS_APPL_STACK_SIZE
	addu	t0, sp
	addu	t0, v0
	la	t1, sys_freemem
	sw	t0, 0(t1)
		 
	/*  C-functions can now be called (memory ready and sp,gp have been set).
	 *  Interrupts are disabled .
	 *  We are using the exception handlers of the bootprom.
	 */

	/*  Call the first C-function. It should never return. If it does, we
	 * consider it an error, and expect v0 to hold the error code.
	 */

	DISP_STR( msg_main )

	li	t0, 4*4
	subu	sp, t0	
	la	t0, c_entry
	jalr	t0
	nop

error:
	/*  Error handling. Display error code (if device for this is available) and
	 *  enter an infinite loop (from init.h)
	 */

	ERROR_HANDLING	
	
END(__reset_handler_end)


/************************************************************************	
 *
 *                          sys_determine_sdram_parms
 *  Description :
 *  -------------
 *
 *  Determine and validate SDRAM size parameters based on SPD device
 *
 *  Parameters :
 *  ------------
 * 
 *  a0 = Max RAM size.
 *  a1 = Max module bank size.
 *  k0 = Platform ID	
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = error code (0 = OK)
 *  v1 = SDRAM device size (in Mbit)
 *  t0 = SDRAM device bank count (not the module bank count)
 *  t1 = Module bank 0 size (possibly adjusted)
 *  t2 = Module bank 1 size (possibly adjusted and possibly 0)
 * 
 ************************************************************************/
LEAF(sys_determine_sdram_parms)

#define RA		s0
#define RAMSIZE_MAX	s1
#define BANKSIZE_MAX	s2
#define DEV_BANKS	s3
#define DEV_SIZE	s4
#define ROWS		s5
#define COLS		s6

	/* s0..s6 used */

	move	RA,	      ra
	move	RAMSIZE_MAX,  a0
	move	BANKSIZE_MAX, a1

	/* Number of Row bits */
	li	a0, SPD_ROWS
	jal	sys_spd_read
	nop
	bne	v0, zero, error_sdram
	nop
	beq	v1, zero, error_sdram	/* No SPD device or row == 0 */
	li	v0, ERROR_SPD	
	move	ROWS, v1
	and	ROWS, SPD_ROWS_A_MSK
	srl	ROWS, SPD_ROWS_A_SHF

	/* Number of Column bits */
	li	a0, SPD_COL
	jal	sys_spd_read
	nop
	bne	v0, zero, error_sdram
	nop
	move	COLS, v1
	and	COLS, COLS, SPD_COL_A_MSK
	srl	COLS, SPD_COL_A_SHF

	/*  Number of SDRAM device banks
	 *  Note : This is the internal bank count of the SDRAM devices, not to
	 *         be confused with the module banks of the SDRAM module
	 */
	li	a0, SPD_DEVICE_BANKS
	jal	sys_spd_read		
	nop
	bne	v0, zero, error_sdram
	nop
	move	DEV_BANKS, v1

	/* SDRAM device width */
	li	a0, SPD_SDRAM_WIDTH
	jal	sys_spd_read	
	nop
	bne	v0, zero, error_sdram
	nop
	and	v1, SPD_SDRAM_WIDTH_W_MSK
	srl	v1, SPD_SDRAM_WIDTH_W_SHF
		
	/* Calc SDRAM device size = 
	 * dev_width * dev_banks * 2 ^ (rows + columns) 
	 */
	addu	t0, ROWS, COLS
	li	t1, 1
	sll	t1, t0
	multu	DEV_BANKS, t1
	MFLO(	DEV_SIZE )
	multu	DEV_SIZE, v1
	MFLO(   DEV_SIZE )

#undef ROWS
#undef COLS

       /* s0..s4 used */

#define BSIZE0		s5
#define BSIZE1		s6
#define MOD_BANKS	s7

	/* s0..s7 used */

	/* Module banks */
	li	a0, SPD_MODULE_BANKS
	jal	sys_spd_read	
	nop
	bne	v0, zero, error_sdram
	nop
	move	MOD_BANKS, v1

	/**** Determine size of bank(s) ****/
	li	a0, SPD_ROW_DENSITY
	jal	sys_spd_read
	nop
	bne	v0, zero, error_sdram
	nop
	beq	v1, zero, error_sdram