piix4.h

MIPS下的boottloader yamon 的源代码

/************************************************************************
 *
 *  piix4.h
 *
 *  Register definitions for Intel PIIX4 South Bridge Device
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/

#ifndef PIIX4_H
#define PIIX4_H

/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <pci.h>

/************************************************************************
 *  PCI registers (word indexed)
 ************************************************************************/

/* Function 0 (32 bit registers) */
#define PIIX4_PCI_GENCFG	0xb0
#define PIIX4_PCI_PIRQRC	0x60
/* Function 0 (8 bit registers)  */
#define PIIX4_PCI_SERIRQC	0x64

/* Function 3 (8 bit registers) */
#define PIIX4_PCI_TOM		0x69
#define PIIX4_PCI_PMREGMISC	0x80
#define PIIX4_PCI_SMBHCFG	0xd2

/************************************************************************
 *  IO register offsets
 ************************************************************************/

/* Function 0 (Bridge) */
#define PIIX4_ELCR1_OFS		0x4d0
#define PIIX4_ELCR2_OFS		0x4d1
#define PIIX4_ICW1M_OFS		0x20
#define PIIX4_ICW2M_OFS		0x21
#define PIIX4_ICW3M_OFS		0x21
#define PIIX4_ICW4M_OFS		0x21
#define PIIX4_ICW1S_OFS		0xa0
#define PIIX4_ICW2S_OFS		0xa1
#define PIIX4_ICW3S_OFS		0xa1
#define PIIX4_ICW4S_OFS		0xa1
#define PIIX4_OCW1M_OFS		0x21
#define PIIX4_OCW1S_OFS		0xa1
#define PIIX4_OCW2M_OFS		0x20
#define PIIX4_OCW2S_OFS		0xa0
#define PIIX4_OCW3M_OFS		0x20
#define PIIX4_OCW3S_OFS		0xa0
#define PIIX4_TMRCNT0_OFS	0x40
#define PIIX4_TMRCNT1_OFS	0x41
#define PIIX4_TMRCNT2_OFS	0x42
#define PIIX4_TCW_OFS		0x43

/* Function 3 (Power Management) */
#define PIIX4_PMSTS_OFS		0x00
#define PIIX4_PMCNTRL_OFS	0x04
#define PIIX4_GPSTS_OFS		0x0c
#define PIIX4_GPEN_OFS		0x0e
#define PIIX4_GLBSTS_OFS	0x18
#define PIIX4_GLBEN_OFS		0x20
#define PIIX4_GLBCTL_OFS	0x28

/* Function 3 (SMB)		 */
#define PIIX4_SMBHSTSTS_OFS	0x0
#define PIIX4_SMBHSTCNT_OFS	0x2
#define PIIX4_SMBHSTCMD_OFS	0x3
#define PIIX4_SMBHSTADD_OFS	0x4
#define PIIX4_SMBHSTDAT0_OFS	0x5


/************************************************************************
 *  Register encodings (PCI is little always little endian)
 ************************************************************************/

#define PIIX4_SMBHCFG_IS_SHF		1
#define PIIX4_SMBHCFG_IS_MSK		(MSK(3) << PIIX4_SMBHCFG_IS_SHF)
#define PIIX4_SMBHCFG_IS_SMI		0
#define PIIX4_SMBHCFG_IS_IRQ9		4

#define PIIX4_SMBHCFG_EN_SHF		0
#define PIIX4_SMBHCFG_EN_MSK		(MSK(1) << PIIX4_SMBHCFG_EN_SHF)
#define PIIX4_SMBHCFG_EN_BIT		PIIX4_SMBHCFG_EN_MSK


#define PIIX4_TOM_TOM_SHF		4
#define PIIX4_TOM_TOM_MSK		(MSK(4) << PIIX4_TOM_TOM_SHF)
#define PIIX4_TOM_TOM_1MB		0
#define PIIX4_TOM_TOM_2MB		1
#define PIIX4_TOM_TOM_3MB		2
#define PIIX4_TOM_TOM_4MB		3
#define PIIX4_TOM_TOM_5MB		4
#define PIIX4_TOM_TOM_6MB		5
#define PIIX4_TOM_TOM_7MB		6
#define PIIX4_TOM_TOM_8MB		7
#define PIIX4_TOM_TOM_9MB		8
#define PIIX4_TOM_TOM_10MB		9
#define PIIX4_TOM_TOM_11MB		10
#define PIIX4_TOM_TOM_12MB		11
#define PIIX4_TOM_TOM_13MB		12
#define PIIX4_TOM_TOM_14MB		13
#define PIIX4_TOM_TOM_15MB		14
#define PIIX4_TOM_TOM_16MB		15



#define PIIX4_SERIRQC_ENABLE_SHF	7
#define PIIX4_SERIRQC_ENABLE_MSK	(MSK(1) << PIIX4_SERIRQC_ENABLE_SHF)
#define PIIX4_SERIRQC_ENABLE_BIT	PIIX4_SERIRQC_ENABLE_MSK
#define PIIX4_SERIRQC_CONT_SHF		6
#define PIIX4_SERIRQC_CONT_MSK		(MSK(1) << PIIX4_SERIRQC_CONT_SHF)
#define PIIX4_SERIRQC_CONT_BIT		PIIX4_SERIRQC_CONT_MSK
#define PIIX4_SERIRQC_FS_SHF		2
#define PIIX4_SERIRQC_FS_MSK		(MSK(4) << PIIX4_SERIRQC_FS_SHF)
#define PIIX4_SERIRQC_FPW_SHF		0
#define PIIX4_SERIRQC_FPW_MSK		(MSK(2) << PIIX4_SERIRQC_FPW_SHF)


#define PIIX4_GENCFG_SERIRQ_SHF		16
#define PIIX4_GENCFG_SERIRQ_MSK		(MSK(1) << PIIX4_GENCFG_SERIRQ_SHF)
#define PIIX4_GENCFG_SERIRQ_BIT		PIIX4_GENCFG_SERIRQ_MSK

#define PIIX4_GENCFG_ISA_SHF		0
#define PIIX4_GENCFG_ISA_MSK		(MSK(1) << PIIX4_GENCFG_ISA_SHF)
#define PIIX4_GENCFG_ISA_BIT		PIIX4_GENCFG_ISA_MSK


#define PIIX4_PMREGMISC_ENABLE_SHF	0
#define PIIX4_PMREGMISC_ENABLE_MSK	(MSK(1) << PIIX4_PMREGMISC_ENABLE_SHF)
#define PIIX4_PMREGMISC_ENABLE_BIT	PIIX4_PMREGMISC_ENABLE_MSK


#define PIIX4_PIRQRC_PCIA_ID_SHF	7
#define PIIX4_PIRQRC_PCIA_ID_MSK	(MSK(1) << PIIX4_PIRQRC_PCIA_ID_SHF)
#define PIIX4_PIRQRC_PCIA_ID_BIT	PIIX4_PIRQRC_PCIA_ID_MSK

#define PIIX4_PIRQRC_PCIA_IR_SHF	0
#define PIIX4_PIRQRC_PCIA_IR_MSK	(MSK(4) << PIIX4_PIRQRC_PCIA_IR_SHF)
#define PIIX4_PIRQRC_PCIA_IR_IRQ3	3
#define PIIX4_PIRQRC_PCIA_IR_IRQ4	4
#define PIIX4_PIRQRC_PCIA_IR_IRQ5	5
#define PIIX4_PIRQRC_PCIA_IR_IRQ6	6
#define PIIX4_PIRQRC_PCIA_IR_IRQ7	7
#define PIIX4_PIRQRC_PCIA_IR_IRQ9	9
#define PIIX4_PIRQRC_PCIA_IR_IRQ10	10
#define PIIX4_PIRQRC_PCIA_IR_IRQ11	11
#define PIIX4_PIRQRC_PCIA_IR_IRQ12	12
#define PIIX4_PIRQRC_PCIA_IR_IRQ14	14
#define PIIX4_PIRQRC_PCIA_IR_IRQ15	15

#define PIIX4_PIRQRC_PCIB_ID_SHF	(7 + 8)
#define PIIX4_PIRQRC_PCIB_ID_MSK	(MSK(1) << PIIX4_PIRQRC_PCIB_ID_SHF)
#define PIIX4_PIRQRC_PCIB_ID_BIT	PIIX4_PIRQRC_PCIB_ID_MSK

#define PIIX4_PIRQRC_PCIB_IR_SHF	(0 + 8)
#define PIIX4_PIRQRC_PCIB_IR_MSK	(MSK(4) << PIIX4_PIRQRC_PCIB_IR_SHF)
#define PIIX4_PIRQRC_PCIB_IR_IRQ3	3
#define PIIX4_PIRQRC_PCIB_IR_IRQ4	4
#define PIIX4_PIRQRC_PCIB_IR_IRQ5	5
#define PIIX4_PIRQRC_PCIB_IR_IRQ6	6
#define PIIX4_PIRQRC_PCIB_IR_IRQ7	7
#define PIIX4_PIRQRC_PCIB_IR_IRQ9	9
#define PIIX4_PIRQRC_PCIB_IR_IRQ10	10
#define PIIX4_PIRQRC_PCIB_IR_IRQ11	11
#define PIIX4_PIRQRC_PCIB_IR_IRQ12	12
#define PIIX4_PIRQRC_PCIB_IR_IRQ14	14
#define PIIX4_PIRQRC_PCIB_IR_IRQ15	15

#define PIIX4_PIRQRC_PCIC_ID_SHF	(7 + 16)
#define PIIX4_PIRQRC_PCIC_ID_MSK	(MSK(1) << PIIX4_PIRQRC_PCIC_ID_SHF)
#define PIIX4_PIRQRC_PCIC_ID_BIT	PIIX4_PIRQRC_PCIC_ID_MSK

#define PIIX4_PIRQRC_PCIC_IR_SHF	(0 + 16)
#define PIIX4_PIRQRC_PCIC_IR_MSK	(MSK(4) << PIIX4_PIRQRC_PCIC_IR_SHF)
#define PIIX4_PIRQRC_PCIC_IR_IRQ3	3
#define PIIX4_PIRQRC_PCIC_IR_IRQ4	4
#define PIIX4_PIRQRC_PCIC_IR_IRQ5	5
#define PIIX4_PIRQRC_PCIC_IR_IRQ6	6
#define PIIX4_PIRQRC_PCIC_IR_IRQ7	7
#define PIIX4_PIRQRC_PCIC_IR_IRQ9	9
#define PIIX4_PIRQRC_PCIC_IR_IRQ10	10
#define PIIX4_PIRQRC_PCIC_IR_IRQ11	11
#define PIIX4_PIRQRC_PCIC_IR_IRQ12	12
#define PIIX4_PIRQRC_PCIC_IR_IRQ14	14
#define PIIX4_PIRQRC_PCIC_IR_IRQ15	15

#define PIIX4_PIRQRC_PCID_ID_SHF	(7 + 24)
#define PIIX4_PIRQRC_PCID_ID_MSK	(MSK(1) << PIIX4_PIRQRC_PCID_ID_SHF)
#define PIIX4_PIRQRC_PCID_ID_BIT	PIIX4_PIRQRC_PCID_ID_MSK

#define PIIX4_PIRQRC_PCID_IR_SHF	(0 + 24)
#define PIIX4_PIRQRC_PCID_IR_MSK	(MSK(4) << PIIX4_PIRQRC_PCID_IR_SHF)
#define PIIX4_PIRQRC_PCID_IR_IRQ3	3
#define PIIX4_PIRQRC_PCID_IR_IRQ4	4
#define PIIX4_PIRQRC_PCID_IR_IRQ5	5
#define PIIX4_PIRQRC_PCID_IR_IRQ6	6
#define PIIX4_PIRQRC_PCID_IR_IRQ7	7
#define PIIX4_PIRQRC_PCID_IR_IRQ9	9
#define PIIX4_PIRQRC_PCID_IR_IRQ10	10
#define PIIX4_PIRQRC_PCID_IR_IRQ11	11
#define PIIX4_PIRQRC_PCID_IR_IRQ12	12
#define PIIX4_PIRQRC_PCID_IR_IRQ14	14
#define PIIX4_PIRQRC_PCID_IR_IRQ15	15



#define PIIX4_ICW1_ICWSEL75_SHF		5
#define PIIX4_ICW1_ICWSEL75_MSK		(MSK(3) << PIIX4_ICW1_ICWSEL75_SHF)
#define PIIX4_ICW1_ICWSEL_SHF		4
#define PIIX4_ICW1_ICWSEL_MSK		(MSK(1) << PIIX4_ICW1_ICWSEL_SHF)
#define PIIX4_ICW1_ICWSEL_BIT		PIIX4_ICW1_ICWSEL_MSK
#define PIIX4_ICW1_SNGL_SHF		1
#define PIIX4_ICW1_SNGL_MSK		(MSK(1) << PIIX4_ICW1_SNGL_SHF)
#define PIIX4_ICW1_SNGL_BIT		PIIX4_ICW1_SNGL_MSK
#define PIIX4_ICW1_ICW4WR_SHF		0
#define PIIX4_ICW1_ICW4WR_MSK		(MSK(1) << PIIX4_ICW1_ICW4WR_SHF)
#define PIIX4_ICW1_ICW4WR_BIT		PIIX4_ICW1_ICW4WR_MSK


#define PIIX4_ICW2_BASE_SHF		3
#define PIIX4_ICW2_BASE_MSK		(MSK(5) << PIIX4_ICW2_BASE_SHF)


#define PIIX4_ICW3M_CAS_SHF		2
#define PIIX4_ICW3M_CAS_MSK		(MSK(1) << PIIX4_ICW3M_CAS_SHF)
#define PIIX4_ICW3M_CAS_BIT		PIIX4_ICW3M_CAS_MSK