sys_api.h

MIPS下的boottloader yamon 的源代码

void 
sys_cpu_dcache_config( 
    UINT32 ds,
    UINT32 dl,
    UINT32 da,
    UINT32 config1_reset );


/************************************************************************
 *
 *                          sys_tlb_lookup
 *  Description :
 *  -------------
 *
 *  Probe TLB for matching entry
 *
 *  Return values :
 *  ---------------
 *
 *  SYS_TLB_NOTFOUND : No match
 *  SYS_TLB_NOTVALID : Match with valid bit cleared, i.e. not valid
 *  SYS_TLB_WP	     : Match with dirty bit cleared, i.e. write-protected
 *  SYS_TLB_OK       : Valid and Dirty entry found
 *
 ************************************************************************/
UINT32
sys_tlb_lookup(
    UINT32 vaddr,		/* Virtual address			*/
    UINT32 *phys,		/* OUT : Physical address		*/
    UINT32 *pagesize );		/* OUT : Pagesize (byte count)		*/


/************************************************************************
 *
 *                          sys_tlb_write
 *  Description :
 *  -------------
 *
 *  Write TLB
 *
 *  data = pointer to array of 5 words
 * 
 *  array[0] = index
 *  array[1] = pagemask
 *  array[2] = entryhi
 *  array[3] = entrylo0
 *  array[4] = entrylo1
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
sys_tlb_write(
    UINT32 *data );


/************************************************************************
 *
 *                          sys_kseg0
 *  Description :
 *  -------------
 *
 *  Determine KSEG0 address corresponding to input address.
 * 
 *  In case input address is TLB mapped, a lookup is performed in the
 *  TLB to determine the physical address. Then, the corresponding
 *  KSEG0 address is calculated.
 *
 *  In case input address is in KSEG1 range, it is converted to KSEG0.
 *
 *  Return values :
 *  ---------------
 *
 *  TRUE if conversion was successfull, otherwise FALSE
 *
 ************************************************************************/
bool
sys_kseg0(
    UINT32 addr,		/* Address to be converted		*/
    UINT32 *kseg0addr );	/* OUT : Converted address		*/


/************************************************************************
 *
 *                          sys_tlb_read
 *  Description :
 *  -------------
 *
 *  Read TLB
 *
 *  data = pointer to array of 4 words. They will be filled with  the
 *         following data :
 *
 *  array[0] = pagemask
 *  array[1] = entryhi
 *  array[2] = entrylo0
 *  array[3] = entrylo1
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
sys_tlb_read(
    UINT32 index,
    UINT32 *data );


/************************************************************************	
 *
 *                          sys_cpu_k0_config
 *  Description :
 *  -------------
 *
 *  Configure K0 field of CP0 CONFIG register
 *
 *  a0 holds the requested K0 setting
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_cpu_k0_config( 
    UINT32 k0 );		/* K0 field to be written		*/


/************************************************************************
 *
 *                          sys_cpu_configurability
 *  Description :
 *  -------------
 *
 *  Determine cpu configurability
 *
 *  Return values :
 *  ---------------
 *
 *  Mask with the following bit definitions :
 *
 *  Bit 0 : Set if MMU may be configured (TLD -> Fixed)
 *  Bit 1 : Set if cache may be downsized
 *
 ************************************************************************/
UINT32 
sys_cpu_configurability( void );
#define SYS_CPU_CONFIGURABILITY_MMU	1
#define SYS_CPU_CONFIGURABILITY_CACHE	2


/************************************************************************
 *
 *                          sys_cpu_config
 *  Description :
 *  -------------
 *
 *  Configure CPU cache/mmu settings
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
sys_cpu_config( 
    bool	       icache,
    bool	       dcache,
    bool	       mmu,
    t_sys_cpu_decoded  *setting );


/************************************************************************
 *
 *                          sys_cpu_mmu_config
 *  Description :
 *  -------------
 *
 *  Configure MMU
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_cpu_mmu_config(
    UINT8  c8 );


/************************************************************************	
 *
 *                          sys_cpu_type
 *  Description :
 *  -------------
 *
 *  Determine whether processor is 32 or 64 bit.
 *
 *  Parameters :
 *  ------------
 *
 *  None
 *
 *  Return values :
 *  ---------------
 *
 *  0 -> 32 bit
 *  1 -> 64 bit
 *
 ************************************************************************/
UINT32 
sys_cpu_type( void );


/************************************************************************
 *
 *                          sys_wait_ms
 *  Description :
 *  -------------
 *
 *  Wait for the specified interval
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
sys_wait_ms(
    UINT32 ms );	/* Interval in milliseconds			*/


/************************************************************************
 *
 *                          sys_reg_addr
 *  Description :
 *  -------------
 *
 *  Calc address from base address, register spacing and register offset.
 *  Also, in case of device with different endianness than CPU, adjust
 *  for endianness.
 *
 *  In case the following is true, the 2 lsb of the address need
 *  to be inverted :
 *
 *     1) Endianness of target and CPU are not the same
 *     3) spacing is 1 byte
 *
 *  Supports spacings of 8 bit and 32 bit (not 16 bit)
 *
 *  Return values :
 *  ---------------
 *
 *  address (void pointer)
 *
 ************************************************************************/
void *
sys_reg_addr(
    bool   target_bigend,	/* TRUE  -> target is big endian.
			           FALSE -> target is little endian.	*/
    UINT8  spacing,		/* spacing of regs in bytes		*/
    void  *base,		/* Base address				*/
    UINT32 offset );		/* Offset scaled down by spacing	*/


/************************************************************************
 *
 *                          sys_enable_int
 *  Description :
 *  -------------
 *
 *  Enable interrupt: set IE in CP0-status.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_enable_int( void );


/************************************************************************
 *
 *                          sys_enable_int_mask
 *  Description :
 *  -------------
 *
 *  Enable specific CPU interrupt.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_enable_int_mask( 
    UINT32 cpu_int );		/* CPU interrupt 0..7			*/


/************************************************************************
 *
 *                          sys_disable_int_mask
 *  Description :
 *  -------------
 *
 *  Disable specific CPU interrupt.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void 
sys_disable_int_mask( 
    UINT32 cpu_int );		/* CPU interrupt 0..7			*/


/************************************************************************
 *
 *                          sys_disable_int
 *  Description :
 *  -------------
 *
 *  Disable interrupt: clear IE in CP0-status.
 *  
 *  Return values :
 *  ---------------
 *
 *  Old IE bit
 *
 ************************************************************************/
UINT32 
sys_disable_int( void );



/************************************************************************
 *
 *                          sys_store_cp0_regs
 *  Description :
 *  -------------
 *
 *  Store the current values of the CP0 registers.
 *  
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
UINT32 
sys_store_cp0_regs(
    t_gdb_regs *context );  /* The CP0 register values will be set      */


/************************************************************************
 *
 *                          sys_decode_compid
 *  Description :
 *  -------------
 *
 *  Map Company ID field of CPO PrId register to string with company name.
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
char *
sys_decode_compid( 
    UINT8 compid );	/* Company ID field of CP0 PRId register	*/


/************************************************************************
 *
 *                          sys_decode_procid
 *  Description :
 *  -------------
 *
 *  Map processor ID field to string hodling the name of the CPU
 *  
 *  Return values :
 *  ---------------
 *
 *  String holding name of CPU
 *
 ************************************************************************/
char *
sys_decode_procid( void );


/************************************************************************
 *
 *                          sys_validate_range
 *  Description :
 *  -------------
 *
 *  Validate address range (alignment, TLB if mapped address, RAM range).
 *
 *  Return values :
 *  ---------------
 *
 *  OK :		    No error
 *  SHELL_ERROR_ALIGN :     Alignment error
 *  SHELL_ERROR_OVERFLOW :  Range overflow
 *  SHELL_ERROR_TLB :       Mapped address with no match in TLB
 *  SHELL_ERROR_TLB_WP :    Write access to mapped write protected address
 *  SHELL_ERROR_RAM_RANGE : Address in unused RAM space
 *
 ************************************************************************/
UINT32
sys_validate_range(
    UINT32 addr,	/* Start address				*/
    UINT32 count,	/* Byte count					*/
    UINT8  size,	/* Access size (number of bytes)		*/
    bool   write );	/* Write access					*/
    

/************************************************************************
 *
 *                          CP0_index_read
 *  Description :
 *  -------------
 *  Read the CP0 register, 'index', ($0).
 *  
 *  Parameters :
 *  ------------
 *  
 *
 *  Return values :
 *  ---------------
 *  Value of the 32 bit CP0 register, 'index'.
 *
 ************************************************************************/
UINT32 CP0_index_read( void ) ;


/************************************************************************
 *
 *                          CP0_random_read
 *  Description :
 *  -------------
 *  Read the CP0 register, 'random', ($1).
 *  
 *  Parameters :
 *  ------------
 *  
 *
 *  Return values :
 *  ---------------
 *  Value of the 32 bit CP0 register, 'random'.
 *
 ************************************************************************/
UINT32 CP0_random_read( void ) ;


/************************************************************************
 *
 *                          CP0_entrylo0_read
 *  Description :
 *  -------------
 *  Read the CP0 register, 'entrylo0', ($2).
 *  
 *  Parameters :
 *  ------------
 *  
 *
 *  Return values :
 *  ---------------
 *  Value of the 32 bit CP0 register, 'entrylo0'.
 *
 ************************************************************************/
UINT32 CP0_entrylo0_read( void ) ;


/************************************************************************
 *
 *                          CP0_entrylo1_read
 *  Description :
 *  -------------
 *  Read the CP0 register, 'entrylo1', ($3).
 *  
 *  Parameters :
 *  ------------
 *  
 *
 *  Return values :
 *  ---------------
 *  Value of the 32 bit CP0 register, 'entrylo1'.
 *
 ************************************************************************/
UINT32 CP0_entrylo1_read( void ) ;


/************************************************************************
 *
 *                          CP0_context_read
 *  Description :
 *  -------------
 *  Read the CP0 register, 'context', ($4).
 *  
 *  Parameters :
 *  ------------
 *  
 *
 *  Return values :