📄 mac_au1000.c
字号:
/************************************************************************
*
* MAC_AU1000.c
*
* The 'MAC_AU1000' module implements the MAC_AU1000
* device driver as an IO device with following services:
*
* 1) init serial device: configure and initialize MAC
* AU1000 driver
* 2) open serial device: register receive handler
* 3) close serial device: not used
* 4) read serial device: poll for received frame
* 5) write serial device: request frame to be transmitted
* 6) ctrl serial device: not used
*
*
*
************************************************************************/
/************************************************************************
* Include files
************************************************************************/
#include <string.h>
#include <stdio.h>
#include <sysdefs.h>
#include <syserror.h>
#include <sysdev.h>
#include <io_api.h>
#include <syscon_api.h>
#include <sys_api.h>
#include <lan_api.h>
#include <MAC_AU1000_api.h>
// #define ETH_DEBUG 1
/************************************************************************
* Constant Definitions
*************************************************************************/
typedef enum
{
MAC0_MINOR_AU1000_DEVICE = 0, /* There are two MACs on the AU1000 */
MAC1_MINOR_AU1000_DEVICE = 1,
/******* ADD NEW MINOR DEVICES JUST BEFORE THIS LINE ONLY ********/
MAC_MINOR_AU1000_DEVICES
} t_MAC_MINOR_AU1000_devices ;
/* PHY definitions */
#ifdef PB1550_CONFIG
#define PHY_ADDRESS 0x1F
#else
#define PHY_ADDRESS 0
#endif
#define PHY_CONTROL_DEFAULT 0x3000
/* TX and RX packet size: fixed to 2048 bytes This will accomodate the worst case
receive size */
#define MAC_AU1000_PACKET_SIZE 2048
/* Number of TX buffers = number of RX buffers = 4 */
#define MAC_AU1000_TX_BUFFERS 4
#define MAC_AU1000_RX_BUFFERS 4
/* To enable the AU1000 MAC tossing */
#define DISABLE_TOSS 0
#define ENABLE_TOSS 1
/* Minimum packet size - 64 is spec but 4 bytes will be taken automatically by FCS */
#define MAC_AU1000_MIN_PACKET_SIZE 60
/************************************************************************
* Macro Definitions
*************************************************************************/
#define IF_ERROR( completion, function ) \
{ \
completion = function ; \
if ( completion != OK ) \
{ \
return( completion ) ; \
} \
}
/* This is a redefinition of reg without appending OFS to the offs definition */
#define MACREG(base,offs) (*((volatile UINT32 *)((UINT32)(base) + offs) ))
#define SET(f) (1<<f) /* set(CSR0_RA) | set(CSR0_PR) */
#define SETV(v,f) ( ( (unsigned int) (v) ) << f ) /* */
#define CLR(f) (0xFFFFFFFF ^ (1<<f)) /* clr(CSR0_RA) & clr(CSR0_PR) */
/************************************************************************
* Type Definitions
*************************************************************************/
/*
* Network device statistics.
*/
typedef struct net_device_stats
{
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
unsigned long tx_timeout_errors;
/* detailed rx_errors: */
unsigned long rx_zero_length_errors;
unsigned long rx_buffer_length_errors;
unsigned long rx_length_errors;
unsigned long rx_pf_errors;
unsigned long rx_cr_errors; /* recved pkt with crc error */
unsigned long rx_db_errors; /* recv'd frame alignment error */
unsigned long rx_fl_errors; /* recv'r fifo overrun */
unsigned long rx_mi_errors;
/* detailed tx_errors */
unsigned long tx_fa_errors;
unsigned long tx_jt_errors;
unsigned long tx_nc_errors;
unsigned long tx_ls_errors;
unsigned long tx_ed_errors;
unsigned long tx_lc_errors;
unsigned long tx_ec_errors;
unsigned long tx_ur_errors;
} t_net_device_stats ;
/* Device context for a AU1000 LAN controller */
typedef struct MAC_AU1000_device
{
/* pointer for the AU1000 LAN controller register set */
UINT32 *pAU1000CtrlRegs;
/* pointer for the AU1000 LAN Enable register set */
UINT32 *pAU1000EnReg;
/* pointer for the AU1000 LAN DMA register set */
UINT32 *pAU1000DMARegs;
/* Rcv buffer Index */
UINT8 NextRcvBufferIndex;
/* Tx buffer index */
UINT8 NextTxmBufferIndex;
UINT32 TxmBuffer[MAC_AU1000_TX_BUFFERS];
UINT32 RcvBuffer[MAC_AU1000_RX_BUFFERS];
UINT8 PhysicalAddress[SYS_MAC_ADDR_SIZE];
/* network statistics */
t_net_device_stats status ;
} t_MAC_AU1000_device ;
/************************************************************************
* MAC AU1000: Base Addresses - This could be moved to SYSCON to be more Yamon
*************************************************************************/
#define MAC0_AU1000_BASE 0xB0500000
#define MAC1_AU1000_BASE 0xB0510000
#define MAC0_AU1000_EN_BASE 0xB0520000
#define MAC1_AU1000_EN_BASE 0xB0520004
#define MAC0_AU1000_DMA_BASE 0xB4004000
#define MAC1_AU1000_DMA_BASE 0xB4004200
#define Au1500_PBUS1_OFFSET 0x01000000 /* offset between PBUS 1 & PBUS 0 */
/************************************************************************
* MAC AU1000: Control Register Relative Addresses
*************************************************************************/
#define MAC_CONTROL 0x0000 /* MAC Control */
#define MAC_ADDRHI 0x0004 /* MAC Address High */
#define MAC_ADDRLO 0x0008 /* MAC Address Low */
#define MAC_MCHASHH 0x000C /* Multicast UpAddr */
#define MAC_MCHASHL 0x0010 /* Multicast LoAddr */
#define MAC_MIICTRL 0x0014 /* MII Address */
#define MAC_MIIDATA 0x0018 /* MII Data */
#define MAC_FLOWCTL 0x001C /* Flow Control */
#define MAC_VLAN1TG 0x0020 /* VLAN1 Tag */
#define MAC_VLAN2TG 0x0024 /* VLAN2 Tag */
/************************************************************************
* MAC AU1000: Enable Register Relative Address
*************************************************************************/
#define MAC_ENABLE 0x0000
/************************************************************************
* MAC AU1000: DMA Register Address Bits (used to construct offset)
*************************************************************************/
#define MAC_DMA_CHAN 9 /* MAC DMA Channel (0 or 1) */
#define MAC_DMA_TXRX 8 /* MAC DMA TxRx (0-Transmit 1-Receive) */
#define MAC_DMA_BUF 4 /* MAC DMA Buffer offset (2 bits) */
#define MAC_DMA_REG 2 /* MAC DMA Register offset
00 - Status
01 - Address/Enable
10 - Length (transmit only)
11 - Reserved */
#define DMA_RECEIVE 1
#define DMA_TRANSMIT 0
#define DMA_LENGTH 2
#define DMA_ADDRESS_EN 1
#define DMA_STATUS 0
/************************************************************************
* MAC AU1000: Register field encodings
*************************************************************************/
/************************************************************************
* MAC AU1000: Control Bit Defnintions
*************************************************************************/
#define MAC_CONTROL_RA 31 /* 0 Receive All incoming packets */
#define MAC_CONTROL_EM 30 /* 0 Data Buffers Endian Mode 1-BE 0-LE */
/* 29-24 Reserved */
#define MAC_CONTROL_DO 23 /* 0 Disable Receive Own (RC-0 DIS-1) */
#define MAC_CONTROL_LM 21 /* 00 Loopback operating mode */
/* b00 - Normal Mode */
/* b01 - Internal Loopback */
/* b10 - External Loopback */
/* b11 - Reserved */
#define MAC_CONTROL_F 20 /* 0 Full Duplex Mode (Full-1 Half-0) */
#define MAC_CONTROL_PM 19 /* 0 Pass All Multicast */
#define MAC_CONTROL_PR 18 /* 1 Promiscuous Mode (PR-1) */
#define MAC_CONTROL_IF 17 /* 0 Inverse Filtering */
#define MAC_CONTROL_PB 16 /* 0 Pass Bad Frames */
#define MAC_CONTROL_HO 15 /* 0 Hash Only Filtering Mode */
/* 14 Reserved */
#define MAC_CONTROL_HP 13 /* 0 Hash Perfect (Imperfect-1 Perf-0) */
#define MAC_CONTROL_LC 12 /* 0 Deferral Check */
#define MAC_CONTROL_DB 11 /* 0 Disable Broadcast Frames */
#define MAC_CONTROL_DR 10 /* 0 Disable Retry */
/* 09 Reserved */
#define MAC_CONTROL_AP 8 /* 0 Automatic Pad Stripping */
#define MAC_CONTROL_BL 6 /* 00 Back Off Limit */
#define MAC_CONTROL_DC 5 /* Deferral Check */
/* 04 Reserved */
#define MAC_CONTROL_TE 3 /* 0 Transmitter Enable */
#define MAC_CONTROL_RE 2 /* 0 Receiver Enable */
/* 01-00 Reserved */
/*********************************************************************\
* 0x14 - MII Address Register *
\*********************************************************************/
/* 31-16 Reserved */
#define MAC_MIICTRL_PHYA 11 /* 00000 5-bit Phy Address */
#define MAC_MIICTRL_MREG 6 /* 00000 5-bit MII Register */
/* 05-02 Reserved */
#define MAC_MIICTRL_MWR 1 /* 0 MII Write (1-Write 0-Read) */
#define MAC_MIICTRL_MBUSY 0 /* 0 MII Busy */
#define MAC_MIICTRL_MBUSY_MASK (1 << MAC_MIICTRL_MBUSY)
/*********************************************************************\
* 0x18 - MII Data Register *
\*********************************************************************/
/* 31-16 Reserved */
#define MAC_MIIDATA_DATA 0 /* FFFF 16-bit MII Data */
/*********************************************************************\
* NEW Au1K MAC Enable - 0xb0520000-MAC0 / 0xb0520004-MAC1 *
\*********************************************************************/
#define MAC_ENABLE_IPG_MIN 7 /* 2 bits: Min IPG bits 0=MAX, 3=960 */
#define MAC_ENABLE_DMARESET 6 /* DMA (ae_b) Reset */
#define MAC_ENABLE_TXEN 5 /* Value is anded with TX_EN */
#define MAC_ENABLE_MIIENAB 4 /* 0-Assert 1-Deassert Rst_T/RxClkN */
#define MAC_ENABLE_NONCAC 3 /* Cacheable bit 0-cacheable 1-non-cache */
#define MAC_ENABLE_DISTOS 2 /* Disable Tossing 0-Toss 1-Disable Toss */
#define MAC_ENABLE_MACINIT 1 /* 0-> Resets MAC, 1-> Enables MAC */
#define MAC_ENABLE_MACCLK 0 /* New Mac Enable Bit Location */
/* Global driver states - the numbers are arbitrary */
#define MAC_AU1000_DRIVER_IS_STOPPED 0x42
#define MAC_AU1000_DRIVER_IS_STARTED 0x44
/************************************************************************
* MAC AU1000: DMA Address/Enable Register Bits
*************************************************************************/
#define MAC_DMA_ADDR 5 /* 27 bits: Address field starting at bit 5 */
#define MAC_DMA_NEXTBUF 2 /* 2 bits: next buffer to be used by DMA*/
#define MAC_DMA_DONE 1 /* MAC DMA Done bit */
#define MAC_DMA_ENABLE 0 /* MAC DMA Enable bit */
#define MAC_DMA_ADDR_MASK 0xFFFFFFE0
#define MAC_DMA_NEXTBUF_MASK (0x3 << MAC_DMA_NEXTBUF)
#define MAC_DMA_DONE_MASK 0x02
#define MAC_DMA_ENABLE_MASK 0x01
#define MAC_DMA_DISABLE_MASK ~MAC_DMA_ENABLE_MASK
#define MAC_DMA_READY_MASK 0x3
/*********************************************************************\
* MAC Transmit Status Bit Fields *
\*********************************************************************/
#define MAC_TRANSMIT_PR 31 /* Packet Retry */
/* 30-14 Reserved */
#define MAC_TRANSMIT_CC 10 /* 4-bit Collision Count */
#define MAC_TRANSMIT_LO 9 /* Late Collision Observed (retried) */
#define MAC_TRANSMIT_DF 8 /* Deferred */
#define MAC_TRANSMIT_UR 7 /* Data Under Run */
#define MAC_TRANSMIT_EC 6 /* Excessive Collisions */
#define MAC_TRANSMIT_LC 5 /* Late Collision */
#define MAC_TRANSMIT_ED 4 /* Excessive Defferal */
#define MAC_TRANSMIT_LS 3 /* Loss of Carrier */
#define MAC_TRANSMIT_NC 2 /* No Carrier */
#define MAC_TRANSMIT_JT 1 /* Jabber Timeout */
#define MAC_TRANSMIT_FA 0 /* Frame Abort */
#define MAC_TRANSMIT_CC_MASK (0xf << MAC_TRANSMIT_CC)
#define MAC_TRANSMIT_UR_MASK (1 << MAC_TRANSMIT_UR)
#define MAC_TRANSMIT_EC_MASK (1 << MAC_TRANSMIT_EC)
#define MAC_TRANSMIT_LC_MASK (1 << MAC_TRANSMIT_LC)
#define MAC_TRANSMIT_ED_MASK (1 << MAC_TRANSMIT_ED)
#define MAC_TRANSMIT_LS_MASK (1 << MAC_TRANSMIT_LS)
#define MAC_TRANSMIT_NC_MASK (1 << MAC_TRANSMIT_NC)
#define MAC_TRANSMIT_JT_MASK (1 << MAC_TRANSMIT_JT)
#define MAC_TRANSMIT_FA_MASK (1 << MAC_TRANSMIT_FA)
/*********************************************************************\
* MAC Receive Status Bit Fields *
\*********************************************************************/
#define MAC_RECEIVE_MI 31 /* Missed Frame */
#define MAC_RECEIVE_PF 30 /* Packet Filter */
#define MAC_RECEIVE_FF 29 /* Filtering Fail */
#define MAC_RECEIVE_BF 28 /* Broadcast Frame */
#define MAC_RECEIVE_MF 27 /* MultiCast Frame */
#define MAC_RECEIVE_UC 26 /* Unsupprted Control Frame */
#define MAC_RECEIVE_CF 25 /* Control Frame */
#define MAC_RECEIVE_LE 24 /* Length Error */
#define MAC_RECEIVE_V2 23 /* VLAN 2 Frame Check */
#define MAC_RECEIVE_V1 22 /* VLAN 1 Frame Check */
#define MAC_RECEIVE_CR 21 /* CRC Error */
#define MAC_RECEIVE_DB 20 /* Dribble Bit */
#define MAC_RECEIVE_ME 19 /* MII Error (MII_Rxer) */
#define MAC_RECEIVE_FT 18 /* Frame Type (1-Ethernet 0-802.3) */
#define MAC_RECEIVE_CS 17 /* Collision Seen */
#define MAC_RECEIVE_FL 16 /* Frame Too Long */
#define MAC_RECEIVE_RF 15 /* Runt Frame */
#define MAC_RECEIVE_WT 14 /* Watch Dog Timeout */
#define MAC_RECEIVE_L 0 /* 14 bit Frame Length */
#define MAC_RECEIVE_MI_MASK (1 << MAC_RECEIVE_MI)
#define MAC_RECEIVE_PF_MASK (1 << MAC_RECEIVE_PF)
#define MAC_RECEIVE_FF_MASK (1 << MAC_RECEIVE_FF)
#define MAC_RECEIVE_BF_MASK (1 << MAC_RECEIVE_BF)
#define MAC_RECEIVE_MF_MASK (1 << MAC_RECEIVE_MF)
#define MAC_RECEIVE_UC_MASK (1 << MAC_RECEIVE_UC)
#define MAC_RECEIVE_CF_MASK (1 << MAC_RECEIVE_CF)
#define MAC_RECEIVE_LE_MASK (1 << MAC_RECEIVE_LE)
#define MAC_RECEIVE_V2_MASK (1 << MAC_RECEIVE_V2)
#define MAC_RECEIVE_V1_MASK (1 << MAC_RECEIVE_V1)
#define MAC_RECEIVE_CR_MASK (1 << MAC_RECEIVE_CR)
#define MAC_RECEIVE_DB_MASK (1 << MAC_RECEIVE_DB)
#define MAC_RECEIVE_ME_MASK (1 << MAC_RECEIVE_ME)
#define MAC_RECEIVE_FT_MASK (1 << MAC_RECEIVE_FT)
#define MAC_RECEIVE_CS_MASK (1 << MAC_RECEIVE_CS)
#define MAC_RECEIVE_FL_MASK (1 << MAC_RECEIVE_FL)
#define MAC_RECEIVE_RF_MASK (1 << MAC_RECEIVE_RF)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -