📄 cpu_s.s
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/************************************************************************
*
* cpu.S
*
* cpu functions
*
*
* ######################################################################
*
* Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved.
*
* Unpublished rights reserved under the Copyright Laws of the United States of
* America.
*
* This document contains information that is proprietary to MIPS Technologies,
* Inc. ("MIPS Technologies"). Any copying, modifying or use of this information
* (in whole or in part) which is not expressly permitted in writing by MIPS
* Technologies or a contractually-authorized third party is strictly
* prohibited. At a minimum, this information is protected under unfair
* competition laws and the expression of the information contained herein is
* protected under federal copyright laws. Violations thereof may result in
* criminal penalties and fines.
* MIPS Technologies or any contractually-authorized third party reserves the
* right to change the information contained in this document to improve
* function, design or otherwise. MIPS Technologies does not assume any
* liability arising out of the application or use of this information. Any
* license under patent rights or any other intellectual property rights owned
* by MIPS Technologies or third parties shall be conveyed by MIPS Technologies
* or any contractually-authorized third party in a separate license agreement
* between the parties.
* The information contained in this document constitutes one or more of the
* following: commercial computer software, commercial computer software
* documentation or other commercial items. If the user of this information, or
* any related documentation of any kind, including related technical data or
* manuals, is an agency, department, or other entity of the United States
* government ("Government"), the use, duplication, reproduction, release,
* modification, disclosure, or transfer of this information, or any related
* documentation of any kind, is restricted in accordance with Federal
* Acquisition Regulation 12.212 for civilian agencies and Defense Federal
* Acquisition Regulation Supplement 227.7202 for military agencies. The use of
* this information by the Government is further restricted in accordance with
* the terms of the license agreement(s) and/or applicable contract terms and
* conditions covering this information from MIPS Technologies or any
* contractually-authorized third party.
*
************************************************************************/
/************************************************************************
* Include files
************************************************************************/
#include <sysdefs.h>
#include <mips.h>
#include <sys_api.h>
/************************************************************************
* Definitions
************************************************************************/
/************************************************************************
* Public variables
************************************************************************/
/************************************************************************
* Static variables
************************************************************************/
/************************************************************************
* Implementation : Public functions
************************************************************************/
/************************************************************************
*
* sys_tlb_lookup
* Description :
* -------------
*
* Probe TLB for matching entry
*
* a0 holds the virtual address.
* a1 holds pointer to an UINT32, which is set to the mapped address.
* a2 holds pointer to an UINT32, which is set to the pagesize if a
* match is found.
*
* Return values :
* ---------------
*
* SYS_TLB_NOTFOUND : No match
* SYS_TLB_NOTVALID : Match with valid bit cleared, i.e. not valid
* SYS_TLB_WP : Match with dirty bit cleared, i.e. write-protected
* SYS_TLB_OK : Valid and Dirty entry found
*
************************************************************************/
LEAF(sys_tlb_lookup)
.set noreorder
/**** Setup EntryHi ****/
/* VPN2 */
li t0, MSK(19) << 13
and t1, a0, t0
/* ASID */
MFC0( t0, C0_ENTRYHI )
li t2, C0_ENTRYHI_ASID_MSK
and t0, t2
or t1, t0
MTC0( t1, C0_ENTRYHI )
/**** Probe ****/
tlbp
NOPS
MFC0( t0, C0_INDEX )
bgez t0, entry_found
nop
/* Not found */
li v0, SYS_TLB_NOTFOUND
jr ra
nop
entry_found:
/* Read entry */
tlbr
NOPS
/* Determine page size */
MFC0( t0, C0_PAGEMASK )
li t1, MSK( C0_PAGEMASK_MASK_SHF )
or t0, t1
addiu t0, 1
srl t0, t0, 1
/* Store result */
sw t0, 0(a2)
/**** Determine mapped address ****/
/* Even/odd page based on Virtual Address bit N,
* where 2^N = pagesize (currently in t0 register).
*/
and t1, t0, a0
beq t1, zero, even_page
nop
odd_page:
MFC0( t1, C0_ENTRYLO1 )
b calc_pfn
nop
even_page:
MFC0( t1, C0_ENTRYLO0 )
calc_pfn:
/* Determine PFN */
srl t2, t1, C0_ENTRYLO0_PFN_SHF
/* Multiply PFN with page size */
multu t2, t0
MFLO( t2 )
/* Add Least Significant Bits of Virtual address */
addiu t0, -1
and t0, a0
or t2, t0
/* Store result */
sw t2, 0(a1)
/* Determine setting of Valid bit */
li t0, C0_ENTRYLO0_V_MSK
and t2, t1, t0
bne t2, zero, tlb_valid
nop
/* Not valid */
li v0, SYS_TLB_NOTVALID
jr ra
nop
tlb_valid :
/* Determine setting of Dirty bit */
li t0, C0_ENTRYLO0_D_MSK
and t2, t1, t0
bne t2, zero, tlb_ok
nop
/* Write protected */
li v0, SYS_TLB_WP
jr ra
nop
tlb_ok :
li v0, SYS_TLB_OK
jr ra
nop
.set reorder
END(sys_tlb_lookup)
/************************************************************************
*
* sys_tlb_write
* Description :
* -------------
*
* Write TLB
*
* a0 = pointer to array of 5 words
*
* array[0] = index
* array[1] = pagemask
* array[2] = entryhi
* array[3] = entrylo0
* array[4] = entrylo1
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF(sys_tlb_write)
.set noreorder
lw t0, 0(a0)
MTC0( t0, C0_INDEX )
lw t0, 4(a0)
MTC0( t0, C0_PAGEMASK )
lw t0, 8(a0)
MTC0( t0, C0_ENTRYHI )
lw t0, 12(a0)
MTC0( t0, C0_ENTRYLO0 )
lw t0, 16(a0)
MTC0( t0, C0_ENTRYLO1 )
tlbwi
/* Done */
jr ra
nop
.set reorder
END(sys_tlb_write)
/************************************************************************
*
* sys_tlb_read
* Description :
* -------------
*
* Read TLB
*
* a0 = index
* a1 = pointer to array of 5 words. They will be filled with the
* following data :
*
* array[0] = pagemask
* array[1] = entryhi
* array[2] = entrylo0
* array[3] = entrylo1
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF(sys_tlb_read)
.set noreorder
MTC0( a0, C0_INDEX )
tlbr
MFC0( t0, C0_PAGEMASK )
sw t0, 0(a1)
MFC0( t0, C0_ENTRYHI )
sw t0, 4(a1)
MFC0( t0, C0_ENTRYLO0 )
sw t0, 8(a1)
MFC0( t0, C0_ENTRYLO1 )
sw t0, 12(a1)
/* Done */
jr ra
nop
.set reorder
END(sys_tlb_read)
/************************************************************************
*
* sys_icache_invalidate_index
* Description :
* -------------
*
* Invalidate I cache line containing specified index
*
* a0 holds the index
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF(sys_icache_invalidate_index)
.set noreorder
ICACHE_INDEX_INVALIDATE_OP(a0,a1)
jr ra
nop
.set reorder
END(sys_icache_invalidate_index)
/************************************************************************
*
* sys_icache_invalidate_addr
* Description :
* -------------
*
* Invalidate I cache line containing specified address
*
* a0 holds the address
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF(sys_icache_invalidate_addr)
.set noreorder
/* Make sure it is cached */
KSEG0A( a0 )
ICACHE_ADDR_INVALIDATE_OP(a0,a1)
jr ra
nop
.set reorder
END(sys_icache_invalidate_addr)
/************************************************************************
*
* sys_dcache_flush_index
* Description :
* -------------
*
* Flush D cache line containing specified index
*
* a0 holds the index
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF(sys_dcache_flush_index)
.set noreorder
.set mips3
cache DCACHE_INDEX_WRITEBACK_INVALIDATE, 0(a0)
.set mips0
sync
jr ra
nop
.set reorder
END(sys_dcache_flush_index)
/************************************************************************
*
* sys_dcache_flush_addr
* Description :
* -------------
*
* Flush D cache line containing specified address
*
* a0 holds the address
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF(sys_dcache_flush_addr)
.set noreorder
/* Make sure it is cached */
KSEG0A( a0 )
.set mips3
cache DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(a0)
.set mips0
sync
jr ra
nop
.set reorder
END(sys_dcache_flush_addr)
/* Functions used simply to jump to corresponding functions
* linked at 0xbfc0xxxx.
*/
.set noreorder
LEAF(sys_determine_icache_linesize)
la t0, sys_determine_icache_linesize_flash
jr t0
nop
END(sys_determine_icache_linesize)
LEAF(sys_determine_icache_lines)
la t0, sys_determine_icache_lines_flash
jr t0
nop
END(sys_determine_icache_lines)
LEAF(sys_determine_icache_assoc)
la t0, sys_determine_icache_assoc_flash
jr t0
nop
END(sys_determine_icache_assoc)
LEAF(sys_determine_dcache_linesize)
la t0, sys_determine_dcache_linesize_flash
jr t0
nop
END(sys_determine_dcache_linesize)
LEAF(sys_determine_dcache_lines)
la t0, sys_determine_dcache_lines_flash
jr t0
nop
END(sys_determine_dcache_lines)
LEAF(sys_determine_dcache_assoc)
la t0, sys_determine_dcache_assoc_flash
jr t0
nop
END(sys_determine_dcache_assoc)
.set reorder
/************************************************************************
*
* sys_enable_int
* Description :
* -------------
*
* Enable interrupt: set IE in CP0-status.
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF(sys_enable_int)
.set noreorder
MFC0( v0, C0_STATUS)
or v0, C0_STATUS_IE_BIT
MTC0( v0, C0_STATUS)
j ra
nop
.set reorder
END(sys_enable_int)
/************************************************************************
*
* sys_disable_int
* Description :
* -------------
*
* UINT32 sys_disable_int( void )
*
* Disable interrupt: clear IE in CP0-status.
*
* Return values :
* ---------------
*
* Old IE bit
*
************************************************************************/
LEAF(sys_disable_int)
.set noreorder
MFC0( v0, C0_STATUS)
li t0, ~C0_STATUS_IE_BIT
nop
and v1, v0, t0
MTC0( v1, C0_STATUS)
li t0, C0_STATUS_IE_MSK
j ra
and v0, t0
.set reorder
END(sys_disable_int)
/************************************************************************
*
* sys_enable_int_mask
* Description :
* -------------
*
* Enable specific interrupt: set IM[x] bit in CP0-status.
*
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