📄 reset_bosporus.s
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sw t1, ic_cfg0clr(t0)
sw t1, ic_cfg1clr(t0)
sw t1, ic_cfg2clr(t0)
sw t1, ic_srcset(t0)
sw t1, ic_assignset(t0)
sw t1, ic_wakeclr(t0)
sw t1, ic_maskclr(t0)
sw t1, ic_risingclr(t0)
sw t1, ic_fallingclr(t0)
sw zero, ic_testbit(t0)
sync
li t0, AU1500_SYS_ADDR
sw zero, sys_freqctrl0(t0)
sw zero, sys_freqctrl1(t0)
sw zero, sys_clksrc(t0)
sw zero, sys_pininputen(t0)
sync
li t0, AU1500_AC97_ADDR
li t1, 0x2
sw t1, ac97_enable(t0)
sync
li t0, AU1500_USBH_ADDR
li t1, usbh_enable
addu t0, t1, t0
sw zero, 0(t0)
sync
li t0, AU1500_USBD_ADDR
sw zero, usbd_enable(t0)
sync
li t0, AU1500_MACEN_ADDR
sw zero, macen_mac0(t0)
sw zero, macen_mac1(t0)
sync
li t0, AU1500_UART0_ADDR
sw zero, uart_enable(t0)
sync
li t0, AU1500_UART3_ADDR
sw zero, uart_enable(t0)
sync
/*
* Step 16) Determine cause of reset
*/
/* wait 10mS to debounce external signals */
li t1, MEM_1MS*10
1: add t1, -1
bne t1, zero, 1b
nop
li t0, AU1500_SYS_ADDR
lw t1, sys_wakesrc(t0)
/* Clear sys_wakemsk to prevent false events */
sw zero, sys_wakemsk(t0)
sync
/* Clear sys_wakesrc */
//sw zero, sys_wakesrc(t0)
sync
/* Check for Hardware Reset */
andi t2, t1, 0x01
bne zero, t2, hardwarereset
nop
/* Check for Sleep Wakeup */
andi t2, t1, 0x02
bne zero, t2, sleepwakeup
nop
/* Assume run-time reset */
beq zero, zero, runtimereset
nop
/********************************************************************/
hardwarereset:
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
/********************************************************************/
runtimereset:
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
/********************************************************************/
sleepwakeup:
#if 0
/*
* Step 1) Initialize SDRAM. The SDRAM must be in self-refresh mode.
*/
bal wakeupSDRAM
nop
/*
* Step 2) Initialize BOARD
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
la t0, AU1500_SYS_ADDR
lw sp, sys_scratch0(t0)
lw ra, sys_scratch1(t0)
jr ra
nop
#else
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
#endif
/********************************************************************/
/*
* This routine initializes the SDRAM controller from Initial
* Power-up Reset or Running Reset.
*/
initSDRAM:
/* Only perform SDRAM init if running from ROM/Flash */
addu t2, ra, zero /* preserve ra */
bal getPC
nop
getPC:
lui t0, 0x1F00 /* ROM/flash address? */
and t1, t0, ra
addu ra, t2, zero /* restore ra */
bne t0, t1, initSDRAMdone
nop
/* wait 1mS before setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
li t0, AU1500_MEM_ADDR
li t1, MEM_SDMODE0
sw t1, mem_sdmode0(t0)
li t1, MEM_SDMODE1
sw t1, mem_sdmode1(t0)
li t1, MEM_SDMODE2
sw t1, mem_sdmode2(t0)
li t1, MEM_SDADDR0
sw t1, mem_sdaddr0(t0)
li t1, MEM_SDADDR1
sw t1, mem_sdaddr1(t0)
li t1, MEM_SDADDR2
sw t1, mem_sdaddr2(t0)
sync
li t1, MEM_SDREFCFG_D
sw t1, mem_sdrefcfg(t0)
sync
sw zero, mem_sdprecmd(t0)
sync
sw zero, mem_sdautoref(t0)
sync
sw zero, mem_sdautoref(t0)
sync
li t1, MEM_SDREFCFG_E
sw t1, mem_sdrefcfg(t0)
sync
li t1, MEM_SDWRMD0
sw t1, mem_sdwrmd0(t0)
sync
li t1, MEM_SDWRMD1
sw t1, mem_sdwrmd1(t0)
sync
li t1, MEM_SDWRMD2
sw t1, mem_sdwrmd2(t0)
sync
/* wait 1mS after setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
initSDRAMdone:
jr ra
nop
/********************************************************************/
wakeupSDRAM:
/*
* With SDRAM in self refresh mode, update the
* ADDR, MODE and refresh registers
*/
li t0, AU1500_MEM_ADDR
li t1, MEM_SDMODE0
sw t1, mem_sdmode0(t0)
li t1, MEM_SDMODE1
sw t1, mem_sdmode1(t0)
li t1, MEM_SDMODE2
sw t1, mem_sdmode2(t0)
li t1, MEM_SDADDR0
sw t1, mem_sdaddr0(t0)
li t1, MEM_SDADDR1
sw t1, mem_sdaddr1(t0)
li t1, MEM_SDADDR2
sw t1, mem_sdaddr2(t0)
sw zero, mem_sdautoref(t0)
li t1, MEM_SDREFCFG_E
sw t1, mem_sdrefcfg(t0)
sync
jr ra
nop
/********************************************************************/
initBOARD:
/*
* External and/or board-specific peripheral initialization
*/
/*
* Establish MUXed pin functionality
*
* CS=0
* USB=1 USBH
* U3=0 UART3
* SRC=0 GPIO6
* EX1=0 GPIO3
* EX0=0 GPIO2
* UR3=0 UART3
* NI2=0 MAC1
* U0=0 UART0
*/
li t0, AU1500_SYS_ADDR
li t1,(1<<15)
sw t1, sys_pinfunc(t0)
/*
* Establish GPIO direction
*
* GPIO0
* GPIO1
* GPIO2
* GPIO3
* GPIO4
* GPIO5
* GPIO6
* GPIO7
* GPIO8
* GPIO9 UART3
* GPIO10 UART3
* GPIO11 UART3
* GPIO12 UART3
* GPIO13 UART3
* GPIO14 UART3
* GPIO15
* GPIO20 UART0
* GPIO23 UART3
* GPIO24 MAC1
* GPIO25 MAC1
* GPIO26 MAC1
* GPIO27 MAC1
* GPIO28 MAC1
*/
li t1,0x00001FFF
sw t1, sys_trioutclr(t0)
li t1, 0x00008000
sw t1, sys_outputclr(t0)
sync
/*
* Establish GPIO2 direction
*
* GPIO200 Output PCI_RST#
* GPIO201 Input PCI 66EN from PCI SLOT
* GPIO202 Output
* GPIO203 Output
* GPIO204 Output
* GPIO205 Output
* GPIO206 Output
* GPIO207 Output
* GPIO208 Output Kendin RST
* GPIO209 Output
* GPIO210 Output
* GPIO211 Output
* GPIO212 Output
* GPIO213 Output
* GPIO214 Output
* GPIO215 Output
*/
li t0, AU1500_GPIO2_ADDR
li t1,3 /* Reset and Clock Enable */
sw t1,gpio2_enable(t0)
sync
li t1,1 /* Clock Enable Only */
sw t1,gpio2_enable(t0)
sync
sw zero,gpio2_inten(t0) /* No Interrupts from GPIO2 */
sync
li t1,(1<<8)|(1<<0) /* 200:output 208:output */
sw t1,gpio2_dir(t0)
sync
li t1,(1<<24)|(1<<8) | (1<<16)|(1<<0) /* PCI RST is inactive */
sw t1,gpio2_output(t0)
sync
/* wait 1mS */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* Assert Kendin/PCI_RST# before PCI clock enabled */
li t0, AU1500_GPIO2_ADDR /* PCI RST is active */
li t1,(1<<24)|(0<<8) | (1<<16)|(0<<0)
sw t1,gpio2_output(t0)
sync
/* wait 1mS */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/*
* Establish CLOCKing
*
* FREQ5: unused
* FREQ4: unused
* FREQ3: unused
* FREQ2: PCI (done below in PCI setup)
* FREQ1: USBH and USBD
* FREQ0: unused
*/
li t0, AU1500_SYS_ADDR
li t1, (1<<12)|(1<<11)|(1<<10)
sw t1, sys_freqctrl0(t0)
li t1, (3<<12)|(1<<11)|(1<<10)|(3<<7)|(1<<6)|(1<<5)
sw t1, sys_clksrc(t0)
sync
/* Setup PCI Host - See Au1500 PCI app note */
/* Enable PCI Clock - Internally generated from AUXPLL/FREQ2 */
li t3, AU1500_GPIO2_ADDR
lw t1, gpio2_pinstate(t3)
andi t2,t1,2 /* M66EN */
beq zero,t2,pci33mhz
li t0, AU1500_SYS_ADDR
pci66mhz: /* actually 64mhz */
lw t2, sys_freqctrl0(t0)
li t1, (2<<22)|(1<<21)|(1<<20) /* div by 6 */
or t1,t1,t2
sw t1, sys_freqctrl0(t0)
lw t2, sys_clksrc(t0)
li t1, (4<<17)|(1<<16)|(0<<15) /* no div */
or t1,t1,t2
sw t1, sys_clksrc(t0)
b pcireset
nop
pci33mhz: /* actually 32mhz */
lw t2, sys_freqctrl0(t0)
li t1, (2<<22)|(1<<21)|(1<<20) /* div by 6 */
or t1,t1,t2
sw t1, sys_freqctrl0(t0)
lw t2, sys_clksrc(t0)
li t1, (4<<17)|(1<<16)|(1<<15) /* div by 2 */
or t1,t1,t2
sw t1, sys_clksrc(t0)
pcireset:
/* De-assert Kendin/PCI_RST# */
li t0, AU1500_GPIO2_ADDR
li t1,(1<<24)|(1<<8) | (1<<16)|(1<<0)
sw t1,gpio2_output(t0)
sync
/* Wait 6 PCI clock cycles */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
sync
/* Configure the PCI interface */
li t0, AU1500_PCI_ADDR
li t1, 0x00000000
sw t1, pci_cmem(t0)
li t1, 0x0000000F
sw t1, pci_config(t0)
li t1, 0xFFFF0000
sw t1, pci_b2bmask_cch(t0)
li t1, 0x03000000
sw t1, pci_b2bbase0_venid(t0)
li t1, 0x03000000
sw t1, pci_b2bbase1_id(t0)
li t1, 0xE0000000
sw t1, pci_mwmask_dev(t0)
li t1, 0x00000000
sw t1, pci_mwbase_rev_ccl(t0)
li t1, 0x02A00356
sw t1, pci_statcmd(t0)
li t1, 0x00000000
sw t1, pci_hdrtype(t0)
li t1, 0x00000008
sw t1, pci_mbar(t0)
li t1, 0x00000000
sw t1, pci_timeout(t0)
sync
jr ra
nop
/********************************************************************/
alldone:
/*
* Prepare to invoke application main()
*/
.set reorder
/********************************************************************/
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