reset_ti1500.s

MIPS下的boottloader yamon 的源代码

	/*
	 * Step 15) Set peripherals to a known state
	 */
	li		t0, AU1500_IC0_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li		t0, AU1500_IC1_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li	t0, AU1500_SYS_ADDR
	sw	zero, sys_freqctrl0(t0)
	sw	zero, sys_freqctrl1(t0)
	sw	zero, sys_clksrc(t0)
	sw	zero, sys_pininputen(t0)
	sync

	li	t0, AU1500_AC97_ADDR
	li	t1, 0x2
	sw	t1, ac97_enable(t0)
	sync

	li	t0, AU1500_USBH_ADDR
	li	t1, usbh_enable
	addu	t0, t1, t0
	sw	zero, 0(t0)
	sync

	li	t0, AU1500_USBD_ADDR
	sw	zero, usbd_enable(t0)
	sync

	li	t0, AU1500_MACEN_ADDR
	sw	zero, macen_mac0(t0)
	sw	zero, macen_mac1(t0)
	sync

	li	t0, AU1500_UART0_ADDR
	sw	zero, uart_enable(t0)
	sync

	li	t0, AU1500_UART3_ADDR
	sw	zero, uart_enable(t0)
	sync


	/*
	 * Step 16) Determine cause of reset
	 */
	/* wait 10mS to debounce external signals */
	li	t1, MEM_1MS*10
1:	add	t1, -1
	bne	t1, zero, 1b
	nop

	li	t0, AU1500_SYS_ADDR
	lw	t1, sys_wakesrc(t0)

	/* Clear sys_wakemsk to prevent false events */
	sw		zero, sys_wakemsk(t0)
	sync

	/* Clear sys_wakesrc */
	//sw	zero, sys_wakesrc(t0)
	sync

	/* Check for Hardware Reset */
	andi	t2, t1, 0x01
	bne	zero, t2, hardwarereset

	/* Check for Sleep Wakeup */
	andi	t2, t1, 0x02
	bne	zero, t2, sleepwakeup
	nop

	/* Assume run-time reset */
	beq	zero, zero, runtimereset
	nop

/********************************************************************/

hardwarereset:

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal	initSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD-specific items
	 */
	bal	initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	beq	zero, zero, alldone
	nop


/********************************************************************/

runtimereset:

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal	initSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD-specific items
	 */
	bal	initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	beq	zero, zero, alldone
	nop


	
/********************************************************************/

sleepwakeup:

#if 0
	/*
	 * Step 1) Initialize SDRAM. The SDRAM must be in self-refresh mode.
	 */
	bal	wakeupSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD-specific items
	 */
	bal	initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	la	t0, AU1500_SYS_ADDR
	lw	sp, sys_scratch0(t0)
	lw	ra, sys_scratch1(t0)

	jr	ra
	nop

#else

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal	initSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD-specific items
	 */
	bal	initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	beq	zero, zero, alldone
	nop
#endif


/********************************************************************/

	/*
	 * This routine initializes the SDRAM controller from Initial
	 * Power-up Reset or Running Reset.
	 */
initSDRAM:

	/* Only perform SDRAM init if running from ROM/Flash */
	addu	t2, ra, zero	/* preserve ra */
    	bal	getPC
    	nop
getPC:
    	lui	t0, 0x1F00      /* ROM/flash address? */
    	and	t1, t0, ra
	addu	ra, t2, zero	/* restore ra */
   	bne	t0, t1, initSDRAMdone
    	nop

	/* wait 1mS before setup */
	li	t1, MEM_1MS
1:	add	t1, -1
	bne	t1, zero, 1b
	nop

	li	t0, AU1500_MEM_ADDR
	li	t1, MEM_SDMODE0
	sw	t1, mem_sdmode0(t0)

	li	t1, MEM_SDMODE1
	sw	t1, mem_sdmode1(t0)

	li	t1, MEM_SDMODE2
	sw	t1, mem_sdmode2(t0)
	
	li	t1, MEM_SDADDR0
	sw	t1, mem_sdaddr0(t0)

	li	t1, MEM_SDADDR1
	sw	t1, mem_sdaddr1(t0)

	li	t1, MEM_SDADDR2
	sw	t1, mem_sdaddr2(t0)

	sync

	li	t1, MEM_SDREFCFG_D
	sw	t1, mem_sdrefcfg(t0)
	sync

	sw	zero, mem_sdprecmd(t0)
	sync

	sw	zero, mem_sdautoref(t0)
	sync

	sw	zero, mem_sdautoref(t0)
	sync

	li	t1, MEM_SDREFCFG_E
	sw	t1, mem_sdrefcfg(t0)
	sync

	li	t1, MEM_SDWRMD0
	sw	t1, mem_sdwrmd0(t0)		
	sync

	li	t1, MEM_SDWRMD1
	sw	t1, mem_sdwrmd1(t0)		
	sync

	li	t1, MEM_SDWRMD2
	sw	t1, mem_sdwrmd2(t0)
	sync

	/* wait 1mS after setup */
	li	t1, MEM_1MS
1:	add	t1, -1
	bne	t1, zero, 1b
	nop

initSDRAMdone:
	jr		ra
	nop

/********************************************************************/

wakeupSDRAM:

	/* ** Assuming that SDRAM is in self refresh mode.  
	All we need to do is update ADDR, MODE 
	and refresh registers *** */

	li	t0, AU1500_MEM_ADDR

	li	t1, MEM_SDMODE0
	sw	t1, mem_sdmode0(t0)

	li	t1, MEM_SDMODE1
	sw	t1, mem_sdmode1(t0)

	li	t1, MEM_SDMODE2
	sw	t1, mem_sdmode2(t0)
	
	li	t1, MEM_SDADDR0
	sw	t1, mem_sdaddr0(t0)

	li	t1, MEM_SDADDR1
	sw	t1, mem_sdaddr1(t0)

	li	t1, MEM_SDADDR2
	sw	t1, mem_sdaddr2(t0)

	sw	zero, mem_sdautoref(t0)

	li	t1, MEM_SDREFCFG_E
	sw	t1, mem_sdrefcfg(t0)

	sync
	jr	ra
	nop

/********************************************************************/

initBOARD:

	/*
	 * External and/or board-specific peripheral initialization
	 */


	/*
	 * Establish MUXed pin functionality
	 *
	 *  CS=0
	 * USB=0 USBH
	 *  U3=0 UART3
	 * SRC=0 GPIO6
	 * EX1=0 GPIO3
	 * EX0=0 GPIO2
	 * UR3=1 UART3
	 * NI2=0 MAC1
	 *  U0=0 UART0
	 */
	li		t0, AU1500_SYS_ADDR
	li		t1,(1<<15)
	sw		t1, sys_pinfunc(t0)

/***************************************************************************/
/*                                                                         */
/*  IOs on Titanium CPU board default settings                             */
/*  ------------------------------------------                             */
/*                                                                         */
/*  GPIO    name        type   default   comments                          */
/*  ---------------------------------------------------------------------  */
/*   00   CF_CTRL2       I        -      CF CD#1                           */
/*   01   CF_CTRL3       I        -      CF CD#2                           */
/*   02   EXT_IO0        I        -      IOs on expansion connector,       */
/*   03   EXT_IO1        I        -      LCD backlight on multimedia board */
/*   04   CF_CTRL8       I        -      CF RDYBSY                         */
/*   05   PHY_CTRL0      I        -      Phy 1 transmit error              */
/*   06   PHY_CTRL1      I        -      Phy 1 receive error               */
/*   07   PHY_CTRL2      I        -      Phy 2 transmit error              */
/*   08   PHY_CTRL3      I        -      Phy 2 receive error               */
/*   09   CF_CTRL9       I        -      CF_INPACK#                        */
/*   10   U3CTS          (UART3)  -      UART3 CTS                         */
/*   11   U3DCD          (UART3)  -      used to monitor RS232_INVALID     */
/*   12   U3RI           (UART3)  -      USB_CTRL1, used to monitor USB OC#*/
/*   13   U3RTS          (UART3)  -      UART3 RTS                         */
/*   14   U3DTR          (UART3)  1      USB_CTRL0, used to switch USB 5V  */
/*   15   PHY_CTRL6      I        -      PHY_INTR#                         */
/*  ---------------------------------------------------------------------  */
/*  Au1500 silicon stepping AB: no IRQs on GPIO 2xx                        */
/*  ---------------------------------------------------------------------  */
/*  200   GPIO200        O        1      startup: 0, connected to PCI reset*/
/*  201   PHY_CTRL5      O        1      PHY FDX (full duplex = 1)         */
/*  202   PCI_SERR       I        -      monitor PCI_SERR by software      */
/*  203   PCI_RST#       I        -      monitor PCI reset by software     */
/*  204   CF_CTRL0       O        1      CF reset                          */
/*  205   CF_CTRL1       O        1      CF CSEL#                          */
/*  206   AUDIO_CTRL0    O        0      audio amp volume clock            */
/*  207   AUDIO_CTRL1    O        0      audio amp volume up/down          */
/*  208   CF_CTRL4       I        -      CF VS1#                           */
/*  209   CF_CTRL5       I        -      CF VS2#                           */
/*  210   CF_CTRL6       I        -      CF BVD1                           */
/*  211   CF_CTRL7       I        -      CF BVD2                           */
/*  212   nc             I        -      not connected, USB_CTRL0 next rev.*/
/*  213   PHY_CTRL4      O        1      Phy low power = 1                 */
/*  214   CF_CTRL10      O        1      CF power switch (0 = on)          */
/*  215   WDI            O        0      watchdog trigger                  */
/*                                                                         */
/***************************************************************************/
	li		t1, 0x000000FF
	sw		t1, sys_trioutclr(t0)
	li		t1, 0x00008000
	sw		t1, sys_outputclr(t0)
	sync

	/* Set GPIO2 direction */
	/* Reset GPIO module */
	li		t0, AU1500_GPIO2_ADDR
	li		t1, 3
	sw		t1, gpio2_enable(t0)
	sync
	li		t1, 1
	sw		t1, gpio2_enable(t0)
	sync

	/* Clear interrupt Enable bits */
	sw		zero,gpio2_inten(t0)
	sync

	/* Set Outputs and Direction */
	/* Also Assert PCI_RST# before PCI clock enabled */

	li		t1, 0x0000E0F3
	sw		t1, gpio2_dir(t0)
	sync		
	li		t1, 0xE0F36032		/* enable and set PCIReset 200 */
	sw		t1, gpio2_output(t0)	/* see table above */
	sync


	/*
	 * Establish CLOCKing
	 *
	 * FREQ5: unused
	 * FREQ4: unused
	 * FREQ3: unused
	 * FREQ2: PCI (done below in PCI setup)
	 * FREQ1: USBH and USBD
	 * FREQ0: unused
	 */
	li		t0, AU1500_SYS_ADDR
	li		t1, (1<<12)|(1<<11)|(1<<10)
	sw		t1, sys_freqctrl0(t0)
	li		t1, (3<<12)|(1<<11)|(1<<10)|(3<<7)|(1<<6)|(1<<5)
	sw		t1, sys_clksrc(t0)
	sync

	/* Setup PCI Host - See Au1500 PCI app note */
	/* Enable PCI Clock - Internally generated from AUXPLL/FREQ2 */
	/* Titanium board forces PCI Clock to 32MHz */
	b		pci33mhz	/* add conditional to 66 here if desired */
	nop


pci66mhz: /* actually 64mhz - routine included but not used */
	lw		t2, sys_freqctrl0(t0)
	li		t1, (2<<22)|(1<<21)|(1<<20) /* div by 6 */
	or		t1, t1, t2
	sw		t1, sys_freqctrl0(t0)
	lw		t2, sys_clksrc(t0)
	li		t1, (4<<17)|(1<<16)|(0<<15) /* no div */
	or		t1, t1, t2
	sw		t1, sys_clksrc(t0)
	b		pcireset
	nop

pci33mhz: /* actually 32mhz */
	lw		t2, sys_freqctrl0(t0)
	li		t1, (2<<22)|(1<<21)|(1<<20) /* div by 6 */
	or		t1, t1, t2
	sw		t1, sys_freqctrl0(t0)
	lw		t2, sys_clksrc(t0)
	li		t1, (4<<17)|(1<<16)|(1<<15) /* div by 2 */
	or		t1, t1, t2
	sw		t1, sys_clksrc(t0)

pcireset:
	/* wait 1mS */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	/* De-assert PCI_RST# */
	li		t0, AU1500_GPIO2_ADDR
	li		t1, 0xE0F36033		/* deassert PCIReset 200 */
	sw		t1, gpio2_output(t0)
	sync

	/* Wait another millisecond - way more than the required time */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop
	sync

	/* Configure the PCI interface */
	li		t0, AU1500_PCI_ADDR

	li		t1, 0x00000000
	sw		t1, pci_cmem(t0)

	li		t1, 0x0000000F
	sw		t1, pci_config(t0)

	li		t1, 0xFFFF0000
	sw		t1, pci_b2bmask_cch(t0)

	li		t1, 0x00000000
	sw		t1, pci_b2bbase0_venid(t0)

	li		t1, 0x00000000
	sw		t1, pci_b2bbase1_id(t0)

	li		t1, 0xE0000000
	sw		t1, pci_mwmask_dev(t0)

	li		t1, 0x00000000
	sw		t1, pci_mwbase_rev_ccl(t0)

	li		t1, 0x02A00356
	sw		t1, pci_statcmd(t0)

	li		t1, 0x00000000
	sw		t1, pci_hdrtype(t0)

	li		t1, 0x00000008
	sw		t1, pci_mbar(t0)

	li		t1, 0x00000000
	sw		t1, pci_timeout(t0)

	/* Take PHYs out of low-power mode */
	li		t0, AU1500_GPIO2_ADDR
	li		t1, 0xE0F34033		/* enable phy */
	sw		t1, gpio2_output(t0)
	sync

	sync
	jr		ra
	nop

/********************************************************************/

alldone:

	/*
	 * Prepare to invoke application main()
	 */
	.set reorder

/********************************************************************/