reset_pb1550.s

MIPS下的boottloader yamon 的源代码

	li		t2, MEM_SDCONFIGB_SDR
	li		t3, MEM_SDMODE_SDR
	li		v0, MEM_MR0_SDR
#else
	lw		t1, MEM_SDCONFIGA(a0)
	lw		t2, MEM_SDCONFIGB(a0)
	lw		t3, MEM_SDMODE(a0)
	lw		v0, MEM_MR0(a0)
#endif
	li		t4, MEM_SDADDR0_SDR
	li		t5, MEM_SDADDR1_SDR
	li		t6, MEM_SDADDR2_SDR

	sw		t1, mem_sdconfiga(t0)
	sync
	sw		t2, mem_sdconfigb(t0)
	sync
	sw		t3, mem_sdmode0(t0)
	sw		t3, mem_sdmode1(t0)
	sw		t3, mem_sdmode2(t0)
	sw		t4, mem_sdaddr0(t0)
	sw		t5, mem_sdaddr1(t0)
	sw		t6, mem_sdaddr2(t0)
	sync

	/*
	 * Initialization per Micron data sheet, page 9:
	 * 0. Power sequence
	 * 1. 100us delay
	 * 2. NOP w/ CKE
	 * 3. PRECHARGE ALL
	 * 4. PRECHARGE ALL
	 * 5. AUTO REFRESH x 2
	 * 6. LOAD MODE REGISTER
	 * Devices are now ready for use.
	 */

	/* NOP w/ CKE */
	lw		t1, mem_sdconfigb(t0)
	li		t2, MEM_SDCONFIGB_BA
	or		t1, t2, t1
	sw		t1, mem_sdconfigb(t0)
	sync

	/* PRECHARGE ALL */
	sw		zero, mem_sdprecmd(t0)
	sync

	/* AUTO REFRESH x 2 */
	sw		zero, mem_sdautoref(t0)
	sync
	sw		zero, mem_sdautoref(t0)
	sync

	/* LOAD MODE REGISTER */
	sw		v0, mem_sdwrmd0(t0)		
	sync
	sw		v0, mem_sdwrmd1(t0)		
	sync
	sw		v0, mem_sdwrmd2(t0)
	sync

	b		initDRAMdone
	nop

initDDR:

	li		t0, AU1550_MEM_ADDR
#ifndef USE_S9
	li		t1, MEM_SDCONFIGA_DDR
	li		t2, MEM_SDCONFIGB_DDR
	li		t3, MEM_SDMODE_DDR
	li		v0, MEM_MR0_DDR
#else
	lw		t1, MEM_SDCONFIGA(a0)
	lw		t2, MEM_SDCONFIGB(a0)
	lw		t3, MEM_SDMODE(a0)
	lw		v0, MEM_MR0(a0)
#endif
	li		t4, MEM_SDADDR0_DDR
	li		t5, MEM_SDADDR1_DDR
	li		t6, MEM_SDADDR2_DDR

	sw		t1, mem_sdconfiga(t0)
	sync
	sw		t2, mem_sdconfigb(t0)
	sync
	sw		t3, mem_sdmode0(t0)
	sw		t3, mem_sdmode1(t0)
	sw		t3, mem_sdmode2(t0)
	sw		t4, mem_sdaddr0(t0)
	sw		t5, mem_sdaddr1(t0)
	sw		t6, mem_sdaddr2(t0)
	sync

	li		v1, MEM_MR1_DDR
	li		a2, MEM_MR2_DDR
	li		a3, MEM_MR3_DDR

	/*
	 * Initialization per Micron data sheet, page 72:
	 * 0. Power sequence
	 * 1. 200us delay
	 * 2. NOP w/ CKE
	 * 3. PRECHARGE ALL
	 * 4. LOAD MODE REGISTER for the extended mode register (normal, not reduced, drive strength)
	 * 5. LOAD MODE REGISTER for the normal mode register (DLL reset activated)
	 * 6. 200 clocks of idle
	 * 7. PRECHARGE ALL
	 * 8. AUTO REFRESH x 2
	 * 9. LOAD MODE REGISTER (DLL reset de-activated)
	 * Devices are now ready for use.
	 */

	/* NOP w/ CKE */
	lw		t1, mem_sdconfigb(t0)
	li		t2, MEM_SDCONFIGB_BA
	or		t1, t2, t1
	sw		t1, mem_sdconfigb(t0)
	sync

	/* PRECHARGE ALL */
	sw		zero, mem_sdprecmd(t0)
	sync

	/* LOAD MODE REGISTER extended mode register 3 */
	sw		a3, mem_sdwrmd0(t0)
	sync
	sw		a3, mem_sdwrmd1(t0)
	sync
	sw		a3, mem_sdwrmd2(t0)
	sync

	/* LOAD MODE REGISTER extended mode register 2 */
	sw		a2, mem_sdwrmd0(t0)
	sync
	sw		a2, mem_sdwrmd1(t0)
	sync
	sw		a2, mem_sdwrmd2(t0)
	sync

	/* LOAD MODE REGISTER extended mode register 1 */
	sw		v1, mem_sdwrmd0(t0)
	sync
	sw		v1, mem_sdwrmd1(t0)
	sync
	sw		v1, mem_sdwrmd2(t0)
	sync

	/* LOAD MODE REGISTER normal mode register DLL reset */
#define MR0_DLL 0x0100
	ori		t1, v0, MR0_DLL
	sw		t1, mem_sdwrmd0(t0)
	sync
	sw		t1, mem_sdwrmd1(t0)
	sync
	sw		t1, mem_sdwrmd2(t0)
	sync

	/* 200 clocks of idle */
	lw		t1, mem_sdconfigb(t0)
	li		t2, MEM_SDCONFIGB_BA
	or		t1, t2, t1
	sw		t1, mem_sdconfigb(t0)
	sync

	/* PRECHARGE ALL */
	sw		zero, mem_sdprecmd(t0)
	sync

	/* AUTO REFRESH x 2 */
	sw		zero, mem_sdautoref(t0)
	sync
	sw		zero, mem_sdautoref(t0)
	sync

	/* LOAD MODE REGISTER normal mode register */
	sw		v0, mem_sdwrmd0(t0)
	sync
	sw		v0, mem_sdwrmd1(t0)
	sync
	sw		v0, mem_sdwrmd2(t0)
	sync

initDRAMdone:
	li		t0, AU1550_MEM_ADDR

	/* Enable refresh */
	lw		t1, mem_sdconfiga(t0)
	li		t2, MEM_SDCONFIGA_E
	or		t1, t2, t1
	sw		t1, mem_sdconfiga(t0)
	sync

	/* wait 1mS after setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	jr		ra
	nop

/********************************************************************/

wakeupDRAM:

	li		t0, PB1550_BCSR_ADDR
	lw		t1, bcsr_whoami(t0)
	sync
	and		t2, t1, PB1550_ID_MSK     
	beq		zero, t2, wakeupDDR
	nop

wakeupSDR:

#ifndef USE_S9
	li		t1, MEM_SDCONFIGA_SDR
	li		t2, MEM_SDCONFIGB_SDR
	li		t3, MEM_SDMODE_SDR
#endif
	li		t4, MEM_SDADDR0_SDR
	li		t5, MEM_SDADDR1_SDR
	li		t6, MEM_SDADDR2_SDR
	b		wakeupDRAMdone
	nop

wakeupDDR:

#ifndef USE_S9
	li		t1, MEM_SDCONFIGA_DDR
	li		t2, MEM_SDCONFIGB_DDR
	li		t3, MEM_SDMODE_DDR
#endif
	li		t4, MEM_SDADDR0_DDR
	li		t5, MEM_SDADDR1_DDR
	li		t6, MEM_SDADDR2_DDR

wakeupDRAMdone:
#ifdef USE_S9
	lw		t1, MEM_SDCONFIGA(a0)
	lw		t2, MEM_SDCONFIGB(a0)
	lw		t3, MEM_SDMODE(a0)
#endif
	li		t0, AU1550_MEM_ADDR
	sw		t1, mem_sdconfiga(t0)
	sync
	sw		t2, mem_sdconfigb(t0)
	sync
	sw		t3, mem_sdmode0(t0)
	sw		t3, mem_sdmode1(t0)
	sw		t3, mem_sdmode2(t0)
	sw		t4, mem_sdaddr0(t0)
	sw		t5, mem_sdaddr1(t0)
	sw		t6, mem_sdaddr2(t0)
	sync

	/* Assert DCKE - bring DDR out of self refresh */
	/* Note that two mem_sdsref are needed since state lost during sleep */
	sw		zero, mem_sdsref(t0)
	sw		zero, mem_sdsref(t0)

	/*
	 * Issue 80ns of NOPs
	 */
	lw		t1, mem_sdconfigb(t0)
	li		t2, MEM_SDCONFIGB_BA
	or		t1, t2, t1
	sw		t1, mem_sdconfigb(t0)
	sync
	
	/*
	 * Perform burst refresh of 8K rows
	 */
	li		t1, 8192
burstrefresh:
	sw		zero, mem_sdautoref(t0)
	bne		zero, t1, burstrefresh
	addi	t1, t1, -1

	/* Enable refresh */
	lw		t1, mem_sdconfiga(t0)
	li		t2, MEM_SDCONFIGA_E
	or		t1, t2, t1
	sw		t1, mem_sdconfiga(t0)
	sync

	jr		ra
	nop

/********************************************************************/

initBOARD:

	/*
	 * External and/or board-specific peripheral initialization
	 */

	/*
	 * Establish MUXed pin functionality
	 *
	 * PSC3=000 SPI 
	 * PSC2=011 SMbus CLK/DATA, GPIO[213:211]
	 * CS=0   EXTCLK0
	 * U3=0	  U3TXD
	 * U1=0	  U1RTS U1TXD
	 * EX1=0  GPIO3
	 * EX0=0  GPIO2
	 * UR3=1  RTS,DTR etc
	 * NI2=0  MAC1
	 * U0=0   U0TXD
	 * S1=0   GPIO17
	 * S0=0   GPIO16
	 */
	li		t0, AU1550_SYS_ADDR
	li		t1, SYS_PINFUNC_PSC2_SM | SYS_PINFUNC_PSC3_I2S | SYS_PINFUNC_U3 | SYS_PINFUNC_MBS1 | SYS_PINFUNC_MBS2
	sw		t1, sys_pinfunc(t0)

	/*
	 * Establish GPIO direction
	 *
	 * GPIO0 Input PCMCIA 0 Interrupt#
	 * GPIO1 Input PCMCIA 1 Interrupt#
	 * GPIO2 EXTCLK0 -- I2S_MCLK
	 * GPIO3 Input DC IRQ#
	 * GPIO4 Input DC DMA_REQ
	 * GPIO5 Input REG DMA_REQ
	 * GPIO6 Input GPIO6_Switch
	 * GPIO7 Input FLASH_BUSY
	 * GPIO8 Output Red LED#
	 * GPIO9  UART3
	 * GPIO10 UART3
	 * GPIO11 UART3
	 * GPIO12 UART3
	 * GPIO13 UART3
	 * GPIO14 UART3
	 * GPIO15 Output Green LED#
	 * GPIO20 UART0
	 * GPIO23 UART3
	 * GPIO24 MAC1
	 * GPIO25 MAC1
	 * GPIO26 MAC1
	 * GPIO27 MAC1
	 * GPIO28 MAC1
	 */
	li		t1,0x000000FB
	sw		t1, sys_trioutclr(t0)
	li		t1, 0x00008000				// Turn on the Green LED
	sw		t1, sys_outputclr(t0)
	sync

	/*
	 * Establish GPIO2 direction
	 *
	 * GPIO200 Output PCI_RST#
	 * GPIO201 Input Undefined
	 * GPIO202 Input Undefined
	 * GPIO203 Input PCMCIA 0 STSCHG
	 * GPIO204 Input AC97 MCLK
	 * GPIO205 Input PCMCIA 1 STSCHG
	 * GPIO206 Output NAND_CS
	 * GPIO207 Input USB OTG
	 * GPIO208 Input USB DEV_RDY
	 * GPIO209 PSC2
	 * GPIO210 PSC2
	 * GPIO211 PSC3
	 * GPIO212 PSC3
	 * GPIO213 PSC3
	 * GPIO214 PSC3
	 * GPIO215 PSC3
	 */
	li		t0, AU1550_GPIO2_ADDR
	li		t1,3
	sw		t1,gpio2_enable(t0)
	sync
	li		t1,1
	sw		t1,gpio2_enable(t0)
	sync
	sw		zero,gpio2_inten(t0)
	sync
	li		t1,(1<<6)|(1<<0)
	sw		t1,gpio2_dir(t0)
	sync
	li		t1,(0<<22)|(0<<16)|(0<<6)|(0<<0)
	sw		t1,gpio2_output(t0)
	sync

	/* Assert PCI_RST# before PCI clock enabled */
	li		t0, PB1550_BCSR_ADDR
	lw		t1,0x14(t0)
	ori		t1,t1,(1<<10) /* EN_GPIO200_RST */
	sw		t1,0x14(t0)
	sync
	li		t0, AU1550_GPIO2_ADDR
	li		t1,(1<<16)|(0<<0)
	sw		t1,gpio2_output(t0)
	sync

	/*
	 * Establish CLOCKing
	 *
	 * FREQ5: unused
	 * FREQ4: unused
	 * FREQ3: unused
	 * FREQ2: PCI (done below in PCI setup)
	 * FREQ1: 48MHz for USBH and USBD
	 * FREQ0: unused
	 */
	li		t0, AU1550_SYS_ADDR
	li		t1, (1<<12)|(1<<11)|(1<<10)
	sw		t1, sys_freqctrl0(t0)
	li		t1, (3<<2)|(1<<1)|(1<<0)
	sw		t1, sys_clksrc(t0)
	sync

	/* Setup PCI Host - See Au1500 PCI app note */
	/* Enable PCI Clock - Internally generated from AUXPLL/FREQ2 */
	li		t0, PB1550_BCSR_ADDR
	lw		t1,0x14(t0)
	andi	t1,t1,1 /* M66EN */
	beq		zero,t1,pci33mhz
	li		t0, AU1550_SYS_ADDR

pci66mhz: /* actually 64mhz */
	lw		t2, sys_freqctrl0(t0)
	li		t1, (2<<22)|(1<<21)|(1<<20) /* div by 6 */
	or		t1,t1,t2
	sw		t1, sys_freqctrl0(t0)
	lw		t2, sys_clksrc(t0)
	li		t1, (4<<17)|(1<<16)|(0<<15) /* no div */
	or		t1,t1,t2
	sw		t1, sys_clksrc(t0)
	b		pcireset
	nop

pci33mhz: /* actually 32mhz */
	lw		t2, sys_freqctrl0(t0)
	li		t1, (2<<22)|(1<<21)|(1<<20) /* div by 6 */
	or		t1,t1,t2
	sw		t1, sys_freqctrl0(t0)
	lw		t2, sys_clksrc(t0)
	li		t1, (4<<17)|(1<<16)|(1<<15) /* div by 2 */
	or		t1,t1,t2
	sw		t1, sys_clksrc(t0)

pcireset:
	/* wait 1mS */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	/* De-assert PCI_RST# */
	li		t0, AU1550_GPIO2_ADDR
	li		t1,(1<<16)|(1<<0)
	sw		t1,gpio2_output(t0)
	sync

	/* Wait 6 PCI clock cycles */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop
	sync

	/* Setup PCI Host - See Au1550 PCI app note */
	/* Enable PCI Clock - On PbAu1550 PCI clock is external and always running */
	/* De-assert PCI_RST# - On PbAu1550 PCI_RST# is handled externally by default */
	/* Wait 6 PCI clock cycles - On PbAu1550 the bootup time meets this criteria */
	li		t0, AU1550_PCI_ADDR
	li		t1, 0x00000000
	sw		t1, pci_cmem(t0)
	li		t1, 0x0008000F
	sw		t1, pci_config(t0)
	li		t1, 0xFFFF0000
	sw		t1, pci_b2bmask_cch(t0)
	li		t1, 0x00000000
	sw		t1, pci_b2bbase0_venid(t0)
	li		t1, 0x00000000
	sw		t1, pci_b2bbase1_id(t0)
	li		t1, 0xE0000000
	sw		t1, pci_mwmask_dev(t0)
	li		t1, 0x00000000
	sw		t1, pci_mwbase_rev_ccl(t0)
	li		t1, 0x02A00356
	sw		t1, pci_statcmd(t0)
	li		t1, 0x00000000
	sw		t1, pci_hdrtype(t0)
	li		t1, 0x00000008
	sw		t1, pci_mbar(t0)
	li		t1, 0x00000000
	sw		t1, pci_timeout(t0)

	/* Take AMD PHYs out of reset */
	li		t0, PB1550_BCSR_ADDR
	li		t1, 3
	sh		t1, 0x0C(t0)

	/* Ensure PCMCIA interface disabled */
	li		t0, PB1550_BCSR_ADDR
	sh		zero, 0x10(t0)

	jr		ra
	nop

/********************************************************************/

alldone:

	/*
	 * Prepare to invoke application main()
	 */
	.set reorder

/********************************************************************/