📄 reset_pb1100.s
字号:
li t1, MEM_STCFG0
sw t1, mem_stcfg0(t0)
li t1, MEM_STTIME0
sw t1, mem_sttime0(t0)
li t1, MEM_STADDR0
sw t1, mem_staddr0(t0)
/* RCE1 */
li t1, MEM_STCFG1
sw t1, mem_stcfg1(t0)
li t1, MEM_STTIME1
sw t1, mem_sttime1(t0)
li t1, MEM_STADDR1
sw t1, mem_staddr1(t0)
/* RCE2 */
li t1, MEM_STCFG2
sw t1, mem_stcfg2(t0)
li t1, MEM_STTIME2
sw t1, mem_sttime2(t0)
li t1, MEM_STADDR2
sw t1, mem_staddr2(t0)
/* RCE3 */
li t1, MEM_STCFG3
sw t1, mem_stcfg3(t0)
li t1, MEM_STTIME3
sw t1, mem_sttime3(t0)
li t1, MEM_STADDR3
sw t1, mem_staddr3(t0)
sync
/*
* Step 15) Set peripherals to a known state
*/
li t0, AU1100_IC0_ADDR
li t1, 0xFFFFFFFF
sw t1, ic_cfg0clr(t0)
sw t1, ic_cfg1clr(t0)
sw t1, ic_cfg2clr(t0)
sw t1, ic_srcset(t0)
sw t1, ic_assignset(t0)
sw t1, ic_wakeclr(t0)
sw t1, ic_maskclr(t0)
sw t1, ic_risingclr(t0)
sw t1, ic_fallingclr(t0)
sw zero, ic_testbit(t0)
sync
li t0, AU1100_IC1_ADDR
li t1, 0xFFFFFFFF
sw t1, ic_cfg0clr(t0)
sw t1, ic_cfg1clr(t0)
sw t1, ic_cfg2clr(t0)
sw t1, ic_srcset(t0)
sw t1, ic_assignset(t0)
sw t1, ic_wakeclr(t0)
sw t1, ic_maskclr(t0)
sw t1, ic_risingclr(t0)
sw t1, ic_fallingclr(t0)
sw zero, ic_testbit(t0)
sync
li t0, AU1100_SYS_ADDR
sw zero, sys_freqctrl0(t0)
sw zero, sys_freqctrl1(t0)
sw zero, sys_clksrc(t0)
sw zero, sys_pininputen(t0)
sync
li t0, AU1100_AC97_ADDR
li t1, 0x2
sw t1, ac97_enable(t0)
sync
li t0, AU1100_USBH_ADDR
li t1, usbh_enable
addu t0, t1, t0
sw zero, 0(t0)
sync
li t0, AU1100_USBD_ADDR
sw zero, usbd_enable(t0)
sync
li t0, AU1100_MACEN_ADDR
sw zero, macen_mac0(t0)
sync
li t0, AU1100_UART0_ADDR
sw zero, uart_enable(t0)
sync
li t0, AU1100_UART3_ADDR
sw zero, uart_enable(t0)
sync
/*
* Step 16) Determine cause of reset
*/
/* wait 10mS to debounce external signals */
li t1, MEM_1MS*10
1: add t1, -1
bne t1, zero, 1b
nop
li t0, AU1100_SYS_ADDR
lw t1, sys_wakesrc(t0)
/* Clear sys_wakemsk to prevent false events */
sw zero, sys_wakemsk(t0)
sync
/* Clear sys_wakesrc */
//sw zero, sys_wakesrc(t0)
sync
/* Check for Hardware Reset */
andi t2, t1, 0x01
bne zero, t2, hardwarereset
/* Check for Sleep Wakeup */
andi t2, t1, 0x02
bne zero, t2, sleepwakeup
nop
/* Assume run-time reset */
beq zero, zero, runtimereset
nop
/********************************************************************/
hardwarereset:
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
/********************************************************************/
runtimereset:
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
/********************************************************************/
sleepwakeup:
/*
* Step 1) Initialize SDRAM. The SDRAM must be in self-refresh mode.
*/
bal wakeupSDRAM
nop
/*
* Step 2) Initialize BOARD
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
la t0, AU1100_SYS_ADDR
lw sp, sys_scratch0(t0)
lw ra, sys_scratch1(t0)
jr ra
nop
/********************************************************************/
/*
* This routine initializes the SDRAM controller from Initial
* Power-up Reset or Running Reset.
*/
initSDRAM:
/* Only perform SDRAM init if running from ROM/Flash */
addu t2, ra, zero /* preserve ra */
bal getPC
nop
getPC:
lui t0, 0x1F00 /* ROM/flash address? */
and t1, t0, ra
addu ra, t2, zero /* restore ra */
bne t0, t1, initSDRAMdone
nop
/* wait 1mS before setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
li t0, AU1100_MEM_ADDR
li t1, MEM_SDMODE0
sw t1, mem_sdmode0(t0)
li t1, MEM_SDMODE1
sw t1, mem_sdmode1(t0)
li t1, MEM_SDADDR0
sw t1, mem_sdaddr0(t0)
li t1, MEM_SDADDR1
sw t1, mem_sdaddr1(t0)
sync
li t1, MEM_SDREFCFG_D
sw t1, mem_sdrefcfg(t0)
sync
sw zero, mem_sdprecmd(t0)
sync
sw zero, mem_sdautoref(t0)
sync
sw zero, mem_sdautoref(t0)
sync
li t1, MEM_SDREFCFG_E
sw t1, mem_sdrefcfg(t0)
sync
li t1, MEM_SDWRMD0
sw t1, mem_sdwrmd0(t0)
sync
li t1, MEM_SDWRMD1
sw t1, mem_sdwrmd1(t0)
sync
/* wait 1mS after setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
initSDRAMdone:
jr ra
nop
/********************************************************************/
wakeupSDRAM:
/*
* SDRAM must be in sleep/self refresh mode. For these SDRAMs,
* must assert CKE, then tRC (70ns) of NOPs, then burst refresh
* of all rows prior to using.
*/
li t0, AU1100_MEM_ADDR
/*
* Enable SDRAM, assert CKE
*/
li t1, MEM_SDMODE0
sw t1, mem_sdmode0(t0)
li t1, MEM_SDMODE1
sw t1, mem_sdmode1(t0)
li t1, MEM_SDMODE2
sw t1, mem_sdmode2(t0)
li t1, MEM_SDADDR0
sw t1, mem_sdaddr0(t0)
li t1, MEM_SDADDR1
sw t1, mem_sdaddr1(t0)
li t1, MEM_SDADDR2
sw t1, mem_sdaddr2(t0)
/*
* Issue 70ns of NOPs
* Must use non-cached KSEG1 address of Flash
*/
li t1, 0xBFC00000
lw t1, 0(t1)
sync
/*
* Perform burst refresh of 4096 rows
*/
li t1, 4096
burstrefresh:
sw zero, mem_sdautoref(t0)
bne zero, t1, burstrefresh
addi t1, t1, -1
/*
* Re-start auto refresh timer
*/
li t1, MEM_SDREFCFG_E
sw t1, mem_sdrefcfg(t0)
sync
jr ra
nop
/********************************************************************/
initBOARD:
/*
* External and/or board-specific peripheral initialization
*/
#define PB1100_BCSR_ADDR 0xAE000000
/*
* Establish MUXed pin functionality
*
* PC=0 PCMCIA signals
* LCD=0 LCD signals
* CS=0
* USB=1 USBH
* U3=0 UART3
* U1=0 UART1
* SRC=0 GPIO6
* EX1=0 GPIO3
* EX0=0 GPIO2
* IRF=0 GPIO15
* UR3=0 GPIO9..14
* I2D=0 GPIO8
* I2S=0 I2S
* NI=0 MAC0
* U0=0 UART0
* IRD=0 IrDA
* A97=0 AC97
* S0=0 SSI0
*/
li t0, AU1100_SYS_ADDR
li t1,(1<<15)
sw t1, sys_pinfunc(t0)
/*
* Establish GPIO direction
*
* GPIO0 Input User defined
* GPIO1 Input User defined
* GPIO2 Input User defined
* GPIO3 Input User defined
* GPIO4 Input User defined
* GPIO5 Input User defined
* GPIO6 Input Switch S22
* GPIO7 Input User defined
* GPIO8 Input Touchscreen PEN_IRQ#
* GPIO9 Input PCMCIA Card Insert#
* GPIO10 Input PCMCIA Card STSCHG#
* GPIO11 Input PCMCIA Card IRQ#
* GPIO12 Input RTC IRQ#
* GPIO13 Input Daughtercard IRQ#
* GPIO14 Input SD0 Insert#
* GPIO15 Input SD1 Insert#
* GPIO16 Input GPIO_HEXT User defined
* GPIO17 Input GPIO_HEXT User defined
* GPIO18 Input GPIO_HEXT User defined
* GPIO19 Input GPIO_HEXT User defined
* GPIO20 Input User defined switch S21 YAMON endian
* GPIO21 Output User defined LED
* GPIO22 Input 2-wire (not setup here)
* GPIO23 Input 2-wire (not setup here)
* GPIO24 MAC0
* GPIO25 MAC0
* GPIO26 MAC0
* GPIO27 MAC0
* GPIO28 MAC0
* GPIO29 I2S
* GPIO30 I2S
* GPIO31 I2S
*/
li t1,0x00DFFFFF
sw t1, sys_trioutclr(t0)
li t1, 0x00200000
sw t1, sys_outputclr(t0)
sync
/*
* Establish GPIO2 direction.
*
* GPIO200 External LCD
* GPIO201 External LCD
* GPIO202 External LCD
* GPIO203 External LCD
* GPIO204 PCMCIA
* GPIO205 PCMCIA
* GPIO206 PCMCIA
* GPIO207 PCMCIA
* GPIO208 SSI0
* GPIO209 SSI0
* GPIO210 SSI0
* GPIO211 IrDA
* GPIO212 UART0
* GPIO213 UART1
* GPIO214 UART3
* GPIO215 MAC0
*
* NOTE: Nothing to do since all GPIO2 pins are dedicated
* to peripherals/interfaces.
*/
/*
* Establish CLOCKing
*
* FREQ5: unused
* FREQ4: unused
* FREQ3: unused
* FREQ2: USBH, USBD, IrDA
* FREQ1: LCD (not setup here)
* FREQ0: unused
*/
li t0, AU1100_SYS_ADDR
li t1, (0<<22)|(1<<21)|(1<<20)
sw t1, sys_freqctrl0(t0)
li t1, (4<<2)|(0<<1)|(0<<0)
sw t1, sys_clksrc(t0)
sync
/* Take LSI PHY out of reset */
li t0, PB1100_BCSR_ADDR
li t1, 1
sh t1, 0x0C(t0)
/* Take SED13806 out of reset */
li t1, 0x80
sh t1, 0x14(t0)
/* Ensure PCMCIA interface disabled */
sh zero, 0x10(t0)
/* Enable DS1693 RTC, clear-out any wakeup events */
li t0, 0xAC000000
lh t1, 0x28(t0) /* 0x0A << 2 */
andi t1, t1, 0x0F
ori t1, t1, 0x30 /* enable, select alternate bank */
sh t1, 0x28(t0)
sync
lh t1, 0x12C(t0) /* 0x4B << 2 */
andi t1, t1, 0xFC /* clear KSE, WIE */
sh t1, 0x12C(t0)
sync
lh t1, 0x128(t0) /* 0x4A << 2 */
ori t1, t1, 0x08 /* set PAB */
sh t1, 0x128(t0)
sync
jr ra
nop
/********************************************************************/
alldone:
/*
* Prepare to invoke application main()
*/
.set reorder
/********************************************************************/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -