📄 reset_db1100.s
字号:
li t1, MEM_STADDR2
sw t1, mem_staddr2(t0)
/* RCE3 */
li t1, MEM_STCFG3
sw t1, mem_stcfg3(t0)
li t1, MEM_STTIME3
sw t1, mem_sttime3(t0)
li t1, MEM_STADDR3
sw t1, mem_staddr3(t0)
sync
/*
* Step 15) Set peripherals to a known state
*/
li t0, AU1100_IC0_ADDR
li t1, 0xFFFFFFFF
sw t1, ic_cfg0clr(t0)
sw t1, ic_cfg1clr(t0)
sw t1, ic_cfg2clr(t0)
sw t1, ic_srcset(t0)
sw t1, ic_assignset(t0)
sw t1, ic_wakeclr(t0)
sw t1, ic_maskclr(t0)
sw t1, ic_risingclr(t0)
sw t1, ic_fallingclr(t0)
sw zero, ic_testbit(t0)
sync
li t0, AU1100_IC1_ADDR
li t1, 0xFFFFFFFF
sw t1, ic_cfg0clr(t0)
sw t1, ic_cfg1clr(t0)
sw t1, ic_cfg2clr(t0)
sw t1, ic_srcset(t0)
sw t1, ic_assignset(t0)
sw t1, ic_wakeclr(t0)
sw t1, ic_maskclr(t0)
sw t1, ic_risingclr(t0)
sw t1, ic_fallingclr(t0)
sw zero, ic_testbit(t0)
sync
li t0, AU1100_SYS_ADDR
sw zero, sys_freqctrl0(t0)
sw zero, sys_freqctrl1(t0)
sw zero, sys_clksrc(t0)
sw zero, sys_pininputen(t0)
sync
li t0, AU1100_AC97_ADDR
li t1, 0x2
sw t1, ac97_enable(t0)
sync
li t0, AU1100_USBH_ADDR
li t1, usbh_enable
addu t0, t1, t0
sw zero, 0(t0)
sync
li t0, AU1100_USBD_ADDR
sw zero, usbd_enable(t0)
sync
li t0, AU1100_MACEN_ADDR
sw zero, macen_mac0(t0)
sync
li t0, AU1100_UART0_ADDR
sw zero, uart_enable(t0)
sync
li t0, AU1100_UART3_ADDR
sw zero, uart_enable(t0)
sync
li t0, AU1100_LCD_ADDR
//sw zero, lcd_control(t0)
sync
/*
* Step 16) Determine cause of reset
*/
/* wait 10mS to debounce external signals */
li t1, MEM_1MS*10
1: add t1, -1
bne t1, zero, 1b
nop
li t0, AU1100_SYS_ADDR
lw t1, sys_wakesrc(t0)
/* Clear sys_wakemsk to prevent false events */
sw zero, sys_wakemsk(t0)
sync
/* Clear sys_wakesrc */
//sw zero, sys_wakesrc(t0)
sync
/* Check for Hardware Reset */
andi t2, t1, 0x01
bne zero, t2, hardwarereset
/* Check for Sleep Wakeup */
andi t2, t1, 0x02
bne zero, t2, sleepwakeup
nop
/* Assume run-time reset */
beq zero, zero, runtimereset
nop
/********************************************************************/
hardwarereset:
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD-specific items
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
/********************************************************************/
runtimereset:
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD-specific items
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
/********************************************************************/
sleepwakeup:
/*
* Step 1) Initialize SDRAM. The SDRAM must be in self-refresh mode.
*/
bal wakeupSDRAM
nop
/*
* Step 2) Initialize BOARD-specific items
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
la t0, AU1100_SYS_ADDR
lw sp, sys_scratch0(t0)
lw ra, sys_scratch1(t0)
jr ra
nop
/********************************************************************/
/*
* This routine initializes the SDRAM controller from Initial
* Power-up Reset or Running Reset.
*/
initSDRAM:
/* Only perform SDRAM init if running from ROM/Flash */
addu t2, ra, zero /* preserve ra */
bal getPC
nop
getPC:
lui t0, 0x1F00 /* ROM/flash address? */
and t1, t0, ra
addu ra, t2, zero /* restore ra */
bne t0, t1, initSDRAMdone
nop
/* wait 1mS before setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
li t0, AU1100_MEM_ADDR
li t1, MEM_SDMODE0
sw t1, mem_sdmode0(t0)
li t1, MEM_SDMODE1
sw t1, mem_sdmode1(t0)
li t1, MEM_SDMODE2
sw t1, mem_sdmode2(t0)
li t1, MEM_SDADDR0
sw t1, mem_sdaddr0(t0)
li t1, MEM_SDADDR1
sw t1, mem_sdaddr1(t0)
li t1, MEM_SDADDR2
sw t1, mem_sdaddr2(t0)
sync
li t1, MEM_SDREFCFG_D
sw t1, mem_sdrefcfg(t0)
sync
sw zero, mem_sdprecmd(t0)
sync
sw zero, mem_sdautoref(t0)
sync
sw zero, mem_sdautoref(t0)
sync
li t1, MEM_SDREFCFG_E
sw t1, mem_sdrefcfg(t0)
sync
li t1, MEM_SDWRMD0
sw t1, mem_sdwrmd0(t0)
sync
li t1, MEM_SDWRMD1
sw t1, mem_sdwrmd1(t0)
sync
li t1, MEM_SDWRMD2
sw t1, mem_sdwrmd2(t0)
sync
/* wait 1mS after setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
initSDRAMdone:
jr ra
nop
/********************************************************************/
wakeupSDRAM:
/*
* SDRAM must be in sleep/self refresh mode. For these SDRAMs,
* must assert CKE, then tRC (70ns) of NOPs, then burst refresh
* of all rows prior to using.
*/
li t0, AU1100_MEM_ADDR
/*
* Enable SDRAM, assert CKE
*/
li t1, MEM_SDMODE0
sw t1, mem_sdmode0(t0)
li t1, MEM_SDMODE1
sw t1, mem_sdmode1(t0)
li t1, MEM_SDMODE2
sw t1, mem_sdmode2(t0)
li t1, MEM_SDADDR0
sw t1, mem_sdaddr0(t0)
li t1, MEM_SDADDR1
sw t1, mem_sdaddr1(t0)
li t1, MEM_SDADDR2
sw t1, mem_sdaddr2(t0)
/*
* Issue 70ns of NOPs (one Flash access is ~120ns)
* Must use non-cached KSEG1 address of Flash
*/
li t1, 0xBFC00000
lw t1, 0(t1)
sync
/*
* Perform burst refresh of 4096 rows
*/
li t1, 4096
burstrefresh:
sw zero, mem_sdautoref(t0)
bne zero, t1, burstrefresh
addi t1, t1, -1
/*
* Re-start auto refresh timer
*/
li t1, MEM_SDREFCFG_E
sw t1, mem_sdrefcfg(t0)
sync
jr ra
nop
/********************************************************************/
initBOARD:
/*
* External and/or board-specific peripheral initialization
*/
#define DB1100_BCSR_ADDR 0xAE000000
/*
* Establish MUXed pin functionality
*
* PC=0 PCMCIA signals
* LCD=0 LCD signals
* CS=0
* USB=1 USBH
* U3=0 UART3
* U1=1 GPIO213
* SRC=0 GPIO6
* EX1=0 GPIO3
* EX0=0 GPIO2
* IRF=0 GPIO15
* UR3=1 UART3
* I2D=0 GPIO8
* I2S=0 I2S
* NI=0 MAC0
* U0=0 UART0
* IRD=0 IrDA
* A97=0 AC97
* S0=1 GPIO210:208
*/
li t0, AU1100_SYS_ADDR
li t1,(1<<15)|(1<<12)|(1<<7)|(1<<0)
sw t1, sys_pinfunc(t0)
/*
* Establish GPIO direction
*
* GPIO0 Input PCMCIA Card 0 Fully inserted
* GPIO1 Input PCMCIA Card 0 STSCHG#
* GPIO2 Input PCMCIA Card 0 IRQ#
* GPIO3 Input PCMCIA Card 1 Fully inserted
* GPIO4 Input PCMCIA Card 1 STSCHG#
* GPIO5 Input PCMCIA Card 1 IRQ#
* GPIO6 Input GPIO6_Switch S2
* GPIO7 Input FLASH_BUSY
* GPIO8 Input Daughtercard IRQ#
* GPIO9 UART3
* GPIO10 UART3
* GPIO11 UART3
* GPIO12 UART3
* GPIO13 UART3
* GPIO14 UART3
* GPIO15 Output Red LED#
* GPIO16 Output Green LED#
* GPIO17 Input GPIO17_Switch S4
* GPIO18 Input User defined
* GPIO19 Input SDIO 0 Fully Inserted
* GPIO20 Input SDIO 1 Fully Inserted
* GPIO21 Input TSC_PENIRQ#
* GPIO22 Input 2-wire (not setup here)
* GPIO23 Input 2-wire (not setup here)
* GPIO24 MAC0
* GPIO25 MAC0
* GPIO26 MAC0
* GPIO27 MAC0
* GPIO28 MAC0
* GPIO29 I2S
* GPIO30 I2S
* GPIO31 I2S
*/
li t1,0x00FE01FF
sw t1, sys_trioutclr(t0)
li t1, 0x00018000
sw t1, sys_outputclr(t0)
sync
/*
* Establish GPIO2 direction
*
* All inputs but...
* GPIO200 LCD
* GPIO201 LCD
* GPIO202 LCD
* GPIO203 LCD
* GPIO204 PCMCIA
* GPIO205 PCMCIA
* GPIO206 PCMCIA
* GPIO207 PCMCIA
* GPIO208 Input ???
* GPIO209 Input ???
* GPIO210 Input ???
* GPIO211 IrDA
* GPIO212 UART0
* GPIO213 Output (user defined)
* GPIO214 UART3
* GPIO215 MAC0
*/
li t0, AU1100_GPIO2_ADDR
li t1,3
sw t1,gpio2_enable(t0)
sync
li t1,1
sw t1,gpio2_enable(t0)
sync
sw zero,gpio2_inten(t0)
sync
li t1,(1<<13)
sw t1,gpio2_dir(t0)
sync
li t1,(1<<29)|(0<<13)
sw t1,gpio2_output(t0)
sync
/*
* Establish CLOCKing
*
* FREQ5: unused
* FREQ4: unused
* FREQ3: unused
* FREQ2: USBH, USBD, IrDA
* FREQ1: LCD (not setup here)
* FREQ0: unused
*/
li t0, AU1100_SYS_ADDR
li t1, (0<<22)|(1<<21)|(1<<20)
sw t1, sys_freqctrl0(t0)
li t1, (4<<2)|(0<<1)|(0<<0)
sw t1, sys_clksrc(t0)
sync
/* Take AMD PHYs out of reset */
li t0, DB1100_BCSR_ADDR
li t1, 1
sw t1, 0x0C(t0)
/* Ensure PCMCIA interface disabled */
li t0, DB1100_BCSR_ADDR
sw zero, 0x10(t0)
sync
jr ra
nop
/********************************************************************/
alldone:
/*
* Prepare to invoke application main()
*/
.set reorder
/********************************************************************/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -