📄 reset_sdv2.s
字号:
li t0, AU1500_IC0_ADDR
li t1, 0xFFFFFFFF
sw t1, ic_cfg0clr(t0)
sw t1, ic_cfg1clr(t0)
sw t1, ic_cfg2clr(t0)
sw t1, ic_srcset(t0)
sw t1, ic_assignset(t0)
sw t1, ic_wakeclr(t0)
sw t1, ic_maskclr(t0)
sw t1, ic_risingclr(t0)
sw t1, ic_fallingclr(t0)
sw zero, ic_testbit(t0)
sync
li t0, AU1500_IC1_ADDR
li t1, 0xFFFFFFFF
sw t1, ic_cfg0clr(t0)
sw t1, ic_cfg1clr(t0)
sw t1, ic_cfg2clr(t0)
sw t1, ic_srcset(t0)
sw t1, ic_assignset(t0)
sw t1, ic_wakeclr(t0)
sw t1, ic_maskclr(t0)
sw t1, ic_risingclr(t0)
sw t1, ic_fallingclr(t0)
sw zero, ic_testbit(t0)
sync
li t0, AU1500_SYS_ADDR
sw zero, sys_freqctrl0(t0)
sw zero, sys_freqctrl1(t0)
sw zero, sys_clksrc(t0)
sw zero, sys_pininputen(t0)
sync
li t0, AU1500_AC97_ADDR
li t1, 0x2
sw t1, ac97_enable(t0)
sync
li t0, AU1500_USBH_ADDR
li t1, usbh_enable
addu t0, t1, t0
sw zero, 0(t0)
sync
li t0, AU1500_USBD_ADDR
sw zero, usbd_enable(t0)
sync
li t0, AU1500_MACEN_ADDR
sw zero, macen_mac0(t0)
sw zero, macen_mac1(t0)
sync
li t0, AU1500_UART0_ADDR
sw zero, uart_enable(t0)
sync
li t0, AU1500_UART3_ADDR
sw zero, uart_enable(t0)
sync
/*
* Step 16) Determine cause of reset
*/
/* wait 10mS to debounce external signals */
li t1, MEM_1MS*10
1: add t1, -1
bne t1, zero, 1b
nop
li t0, AU1500_SYS_ADDR
lw t1, sys_wakesrc(t0)
/* Clear sys_wakemsk to prevent false events */
sw zero, sys_wakemsk(t0)
sync
/* Clear sys_wakesrc */
//sw zero, sys_wakesrc(t0)
sync
/* Check for Hardware Reset */
andi t2, t1, 0x01
bne zero, t2, hardwarereset
/* Check for Sleep Wakeup */
andi t2, t1, 0x02
bne zero, t2, sleepwakeup
nop
/* Assume run-time reset */
beq zero, zero, runtimereset
nop
/********************************************************************/
hardwarereset:
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD-specific items
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
/********************************************************************/
runtimereset:
/*
* Step 1) Initialize SDRAM
*/
bal initSDRAM
nop
/*
* Step 2) Initialize BOARD-specific items
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
beq zero, zero, alldone
nop
/********************************************************************/
sleepwakeup:
/*
* Step 1) Initialize SDRAM. The SDRAM must be in self-refresh mode.
*/
bal wakeupSDRAM
nop
/*
* Step 2) Initialize BOARD-specific items
*/
bal initBOARD
nop
/*
* Step 3) Invoke application
*/
la t0, AU1500_SYS_ADDR
lw sp, sys_scratch0(t0)
lw ra, sys_scratch1(t0)
jr ra
nop
/********************************************************************/
/*
* This routine initializes the SDRAM controller from Initial
* Power-up Reset or Running Reset.
*/
initSDRAM:
/* Only perform SDRAM init if running from ROM/Flash */
addu t2, ra, zero /* preserve ra */
bal getPC
nop
getPC:
lui t0, 0x1F00 /* ROM/flash address? */
and t1, t0, ra
addu ra, t2, zero /* restore ra */
bne t0, t1, initSDRAMdone
nop
/* wait 1mS before setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
li t0, AU1500_MEM_ADDR
li t1, MEM_SDMODE0
sw t1, mem_sdmode0(t0)
li t1, MEM_SDMODE1
sw t1, mem_sdmode1(t0)
li t1, MEM_SDMODE2
sw t1, mem_sdmode2(t0)
li t1, MEM_SDADDR0
sw t1, mem_sdaddr0(t0)
li t1, MEM_SDADDR1
sw t1, mem_sdaddr1(t0)
li t1, MEM_SDADDR2
sw t1, mem_sdaddr2(t0)
sync
li t1, MEM_SDREFCFG_D
sw t1, mem_sdrefcfg(t0)
sync
sw zero, mem_sdprecmd(t0)
sync
sw zero, mem_sdautoref(t0)
sync
sw zero, mem_sdautoref(t0)
sync
li t1, MEM_SDREFCFG_E
sw t1, mem_sdrefcfg(t0)
sync
li t1, MEM_SDWRMD0
sw t1, mem_sdwrmd0(t0)
sync
li t1, MEM_SDWRMD1
sw t1, mem_sdwrmd1(t0)
sync
li t1, MEM_SDWRMD2
sw t1, mem_sdwrmd2(t0)
sync
/* wait 1mS after setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
initSDRAMdone:
jr ra
nop
/********************************************************************/
wakeupSDRAM:
/*
* SDRAM must be in sleep/self refresh mode. For these SDRAMs,
* must assert CKE, then tRC (70ns) of NOPs, then burst refresh
* of all rows prior to using.
*/
li t0, AU1500_MEM_ADDR
/*
* Enable SDRAM, assert CKE
*/
li t1, MEM_SDMODE0
sw t1, mem_sdmode0(t0)
li t1, MEM_SDMODE1
sw t1, mem_sdmode1(t0)
li t1, MEM_SDMODE2
sw t1, mem_sdmode2(t0)
li t1, MEM_SDADDR0
sw t1, mem_sdaddr0(t0)
li t1, MEM_SDADDR1
sw t1, mem_sdaddr1(t0)
li t1, MEM_SDADDR2
sw t1, mem_sdaddr2(t0)
/*
* Issue 70ns of NOPs (one Flash access is ~120ns)
* Must use non-cached KSEG1 address of Flash
*/
li t1, 0xBFC00000
lw t1, 0(t1)
sync
/*
* Perform burst refresh of 8192 rows
*/
li t1, 8192
burstrefresh:
sw zero, mem_sdautoref(t0)
bne zero, t1, burstrefresh
addi t1, t1, -1
/*
* Re-start auto refresh timer
*/
li t1, MEM_SDREFCFG_E
sw t1, mem_sdrefcfg(t0)
sync
jr ra
nop
/********************************************************************/
initBOARD:
/*
* External and/or board-specific peripheral initialization
*/
/*
* Establish MUXed pin functionality
*
* CS=0
* USB=1 USBH
* U3=0 UART3
* SRC=0 GPIO6
* EX1=0 GPIO3
* EX0=0 GPIO2
* UR3=0 GPIO[14:9]
* NI2=0 MAC1
* U0=0 UART0
*/
li t0, AU1500_SYS_ADDR
li t1, (1<<15)
sw t1, sys_pinfunc(t0)
/*
* Establish GPIO direction
*
* GPIO0 Input Power-on / suspend push-button switch
* GPIO1 Input Up push-button switch
* GPIO2 Input Next push-button switch
* GPIO3 Input Prev push-button switch
* GPIO4 Input Down push-button switch
* GPIO5 Input Enter push-button switch
* GPIO6 Input Mip push-button switch
* GPIO7 Input Audio codec PENDOWN touchscreen
* GPIO8 Input Audio codec IRQ
* GPIO9 Input Local app push-button switch
* GPIO10 Input Back push-button switch
* GPIO11 Input More push-button switch
* GPIO12 Input Volume Down push-button switch
* GPIO13 Input Volume Up push-button switch
* GPIO14 Input FLASH_BUSY
* GPIO15 Input Run Test (for mira) n/c
* GPIO20 Output UART0 transmit
* GPIO23 Output UART3 transmit
* GPIO24 Input n/c
* GPIO25 Input n/c
* GPIO26 Input n/c
* GPIO27 Input n/c
* GPIO28 Input n/c
*/
li t1,0x1F00FFFF
sw t1, sys_trioutclr(t0)
li t1, 0x00000000
sw t1, sys_outputclr(t0)
sync
/*
* Establish GPIO2 direction
*
* GPIO200 Output PCI_RST# asserted
* GPIO201 Output PCI_Clock_Run# deasserted
* GPIO202 Input PCI_Power Management Event#
* GPIO203 Input Mini-PCI Active#
* GPIO204 Input Battery Charger IRQ#
* GPIO205 Input Head phones plugged in
* GPIO206 Input Docked#
* GPIO207 Input MCE#
* GPIO208 Input Smart Card Interface IRQ#
* GPIO209 Output Speakers Off#
* GPIO210 Output Software Power Off
* GPIO211 Output PHY_RST# deasserted
* GPIO212 Output LAN_LED yellow# asserted
* GPIO213 Output LAN_LED green# asserted
* GPIO214 Output PWR_LED yellow# asserted
* GPIO215 Output PWR_LED green# asserted
*/
li t0, AU1500_GPIO2_ADDR
li t1,0xfe03
sw t1,gpio2_dir(t0)
sync
li t1,0xfe030a02
sw t1,gpio2_output(t0)
sync
li t1,1
sw t1,gpio2_enable(t0)
sync
sw zero,gpio2_inten(t0)
sync
/*
* Assert PCI_RST# before PCI clock enabled
*/
li t1,0x00010000
sw t1,gpio2_output(t0)
sync
/*
* Establish CLOCKing
*
* FREQ5: unused
* FREQ4: unused
* FREQ3: unused
* FREQ2: PCI (done below in PCI setup)
* FREQ1: USBH and USBD
* FREQ0: unused
*/
li t0, AU1500_SYS_ADDR
li t1, (1<<12)|(1<<11)|(1<<10)
sw t1, sys_freqctrl0(t0)
li t1, (3<<12)|(1<<11)|(1<<10)|(3<<7)|(1<<6)|(1<<5)
sw t1, sys_clksrc(t0)
sync
/* Setup PCI Host - See Au1500 PCI app note */
/* Enable PCI Clock - Internally generated from AUXPLL/FREQ2 */
pci33mhz: /* actually 32mhz */
lw t2, sys_freqctrl0(t0)
li t1, (2<<22)|(1<<21)|(1<<20) /* div by 6 */
or t1,t1,t2
sw t1, sys_freqctrl0(t0)
lw t2, sys_clksrc(t0)
li t1, (4<<17)|(1<<16)|(1<<15) /* div by 2 */
or t1,t1,t2
sw t1, sys_clksrc(t0)
pcireset:
/* wait 1mS */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* Deassert PCI_RST# */
li t0, AU1500_GPIO2_ADDR
li t1,0x00010001
sw t1,gpio2_output(t0)
sync
/* Wait 6 PCI clock cycles */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
sync
/* Configure the PCI interface */
li t0, AU1500_PCI_ADDR
li t1, 0x00000000
sw t1, pci_cmem(t0)
li t1, 0x0000000F
sw t1, pci_config(t0)
li t1, 0xFFFF0000
sw t1, pci_b2bmask_cch(t0)
li t1, 0x00000000
sw t1, pci_b2bbase0_venid(t0)
li t1, 0x00000000
sw t1, pci_b2bbase1_id(t0)
li t1, 0xE0000000
sw t1, pci_mwmask_dev(t0)
li t1, 0x00000000
sw t1, pci_mwbase_rev_ccl(t0)
li t1, 0x02A00356
sw t1, pci_statcmd(t0)
li t1, 0x00000000
sw t1, pci_hdrtype(t0)
li t1, 0x00000008
sw t1, pci_mbar(t0)
li t1, 0x00000000
sw t1, pci_timeout(t0)
sync
jr ra
nop
/********************************************************************/
alldone:
/*
* Prepare to invoke application main()
*/
.set reorder
/********************************************************************/
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