reset_hydrogen3.s

MIPS下的boottloader yamon 的源代码

	sw		t1, mem_sttime3(t0)
	li		t1, MEM_STADDR3
	sw		t1, mem_staddr3(t0)

	sync

	/*
	 * Step 15) Set peripherals to a known state
	 */
	li		t0, AU1100_IC0_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li		t0, AU1100_IC1_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li		t0, AU1100_SYS_ADDR
	sw		zero, sys_freqctrl0(t0)
	sw		zero, sys_freqctrl1(t0)
	sw		zero, sys_clksrc(t0)
	sw		zero, sys_pininputen(t0)
	sync

	li		t0, AU1100_AC97_ADDR
	li		t1, 0x2
	sw		t1, ac97_enable(t0)
	sync

	li		t0, AU1100_USBH_ADDR
	li		t1, usbh_enable
	addu	t0, t1, t0
	sw		zero, 0(t0)
	sync

	li		t0, AU1100_USBD_ADDR
	sw		zero, usbd_enable(t0)
	sync

	li		t0, AU1100_MACEN_ADDR
	sw		zero, macen_mac0(t0)
	sync

	li		t0, AU1100_UART0_ADDR
	sw		zero, uart_enable(t0)
	sync

	li		t0, AU1100_UART3_ADDR
	sw		zero, uart_enable(t0)
	sync


	/*
	 * Step 16) Determine cause of reset
	 */
	/* wait 10mS to debounce external signals */
	li		t1, MEM_1MS*10
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1100_SYS_ADDR
	lw		t1, sys_wakesrc(t0)

	/* Clear sys_wakemsk to prevent false events */
	sw		zero, sys_wakemsk(t0)
	sync

	/* Clear sys_wakesrc */
	//sw		zero, sys_wakesrc(t0)
	sync

	/* Check for Hardware Reset */
	andi	t2, t1, 0x01
	bne		zero, t2, hardwarereset

	/* Check for Sleep Wakeup */
	andi	t2, t1, 0x02
	bne		zero, t2, sleepwakeup
	nop

	/* Assume run-time reset */
	beq		zero, zero, runtimereset
	nop

/********************************************************************/

hardwarereset:

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal		initSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD-specific items
	 */
	bal		initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	beq		zero, zero, alldone
	nop


/********************************************************************/

runtimereset:

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal		initSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD-specific items
	 */
	bal		initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	beq		zero, zero, alldone
	nop


/********************************************************************/

sleepwakeup:

	/*
	 * Step 1) Initialize SDRAM. The SDRAM must be in self-refresh mode.
	 */
	bal		wakeupSDRAM	
	nop

	/*
	 * Step 2) Initialize BOARD-specific items
	 */
	bal		initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	la		t0, AU1100_SYS_ADDR
	lw		sp, sys_scratch0(t0)
	lw		ra, sys_scratch1(t0)

	jr		ra
	nop

/********************************************************************/

	/*
	 * This routine initializes the SDRAM controller from Initial
	 * Power-up Reset or Running Reset.
	 */
initSDRAM:

	/* Only perform SDRAM init if running from ROM/Flash */
	addu	t2, ra, zero	/* preserve ra */
    bal		getPC
    nop
getPC:
    lui		t0, 0x1F00      /* ROM/flash address? */
    and		t1, t0, ra
	addu	ra, t2, zero	/* restore ra */
    bne		t0, t1, initSDRAMdone
    nop

	/* wait 1mS before setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1100_MEM_ADDR
	li		t1, MEM_SDMODE0
	sw		t1, mem_sdmode0(t0)

	li		t1, MEM_SDMODE1
	sw		t1, mem_sdmode1(t0)

	li		t1, MEM_SDMODE2
	sw		t1, mem_sdmode2(t0)
	
	li		t1, MEM_SDADDR0
	sw		t1, mem_sdaddr0(t0)

	li		t1, MEM_SDADDR1
	sw		t1, mem_sdaddr1(t0)

	li		t1, MEM_SDADDR2
	sw		t1, mem_sdaddr2(t0)

	sync

	li		t1, MEM_SDREFCFG_D
	sw		t1, mem_sdrefcfg(t0)
	sync

	sw		zero, mem_sdprecmd(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	li		t1, MEM_SDREFCFG_E
	sw		t1, mem_sdrefcfg(t0)
	sync

	li		t1, MEM_SDWRMD0
	sw		t1, mem_sdwrmd0(t0)		
	sync

	li		t1, MEM_SDWRMD1
	sw		t1, mem_sdwrmd1(t0)		
	sync

	li		t1, MEM_SDWRMD2
	sw		t1, mem_sdwrmd2(t0)
	sync

	/* wait 1mS after setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

initSDRAMdone:
	jr		ra
	nop

/********************************************************************/

wakeupSDRAM:

	/*
	 * SDRAM must be in sleep/self refresh mode. For these SDRAMs,
	 * must assert CKE, then tRC of NOPs, then burst refresh of all
	 * rows prior to using.
	 */
	li		t0, AU1100_MEM_ADDR

	/*
	 * Enable SDRAM, assert CKE
	 */
	li		t1, MEM_SDMODE0
	sw		t1, mem_sdmode0(t0)

	li		t1, MEM_SDMODE1
	sw		t1, mem_sdmode1(t0)

	li		t1, MEM_SDMODE2
	sw		t1, mem_sdmode2(t0)
	
	li		t1, MEM_SDADDR0
	sw		t1, mem_sdaddr0(t0)

	li		t1, MEM_SDADDR1
	sw		t1, mem_sdaddr1(t0)

	li		t1, MEM_SDADDR2
	sw		t1, mem_sdaddr2(t0)

	/*
	 * Issue tRC of NOPs (one Flash access is ~120ns)
	 * Must use non-cached KSEG1 address of Flash
	 */
	li		t1, 0xBFC00000
	lw		t1, 0(t1)
	sync
	
	/*
	 * Perform burst refresh of all rows
	 */
	li		t1, 8192
burstrefresh:
	sw		zero, mem_sdautoref(t0)
	bne		zero, t1, burstrefresh
	addi	t1, t1, -1

	/*
	 * Re-start auto refresh timer
	 */
	li		t1, MEM_SDREFCFG_E
	sw		t1, mem_sdrefcfg(t0)
	sync

	jr		ra
	nop


/********************************************************************/

initBOARD:

	/*
	 * External and/or board-specific peripheral initialization
	 */

	/*
	 * Establish MUXed pin functionality
	 *
	 *  PC=0 PCMCIA signals
	 * LCD=1 GPIO203:200
	 *  CS=0
	 * USB=0 USBD
	 *  U3=1 GPIO214
	 *  U1=1 GPIO213
	 * SRC=0 GPIO6
	 * EX1=0 GPIO3
	 * EX0=0 GPIO2
	 * IRF=1 IRFIRSEL
	 * UR3=0 GPIO9..14
	 * I2D=0 GPIO8
	 * I2S=1 GPIO31:29
	 *  NI=0 MAC0
	 *  U0=0 UART0
	 * IRD=0 IrDA
	 * A97=0 AC97
	 *  S0=1 GPIO210:208
	 */
	li		t0, AU1100_SYS_ADDR
	li		t1, 0x00027121
	sw		t1, sys_pinfunc(t0)
	sync

	/*
	 * Establish GPIO direction
	 *
	 * GPIO0 Input CRADLE_DET
	 * GPIO1 Input SELECT
	 * GPIO2 Input BUTTON_1
	 * GPIO3 Input BUTTON_2
	 * GPIO4 Input EXTPWR_BUFF
	 * GPIO5 Input PENIRQ
	 * GPIO6 Input SwiTCH S1
	 * GPIO7 Input BUTTON_3
	 * GPIO8 Input BUTTON_4
	 * GPIO9  Input LEFT
	 * GPIO10 Input DOWN
	 * GPIO11 Input RIGHT
	 * GPIO12 Input UP
	 * GPIO13 Output IRMODE
	 * GPIO14 I/O MMC_MODE
	 * GPIO15 IRFIRSEL
	 * GPIO16 Input SD_CD
	 * GPIO17 Input SD_WP
	 * GPIO18 Output LCD_GATE_EN
	 * GPIO19 Output CHARGE_EN
	 * GPIO20 Output AMP_PD
	 * GPIO21 Input BUF_CFRDYBSY
	 * GPIO22 Input CF_DETECT
	 * GPIO23 n/a pulled low
	 * GPIO24 MAC0
	 * GPIO25 MAC0
	 * GPIO26 MAC0
	 * GPIO27 MAC0
	 * GPIO28 MAC0
	 * GPIO29 Input AC97_BUSY
	 * GPIO30 n/a pulled low
	 * GPIO31 n/a pulled low
	 */
	li		t1, 0x00631FFF
	sw		t1, sys_trioutclr(t0)
	li		t1, 0x000c2000
	sw		t1, sys_outputclr(t0)
	li 		t1, 0x00100000
	sw		t1, sys_outputset(t0)
	sw		zero, sys_pininputen(t0)
	sync

	/*
	 * Establish GPIO2 direction.
	 *
	 * GPIO200 Output AUCF_RESET
	 * GPIO201 Output CF_POWER
	 * GPIO202 Output LED0
	 * GPIO203 Output LED1
	 * GPIO204 PCMCIA
	 * GPIO205 PCMCIA
	 * GPIO206 PCMCIA
	 * GPIO207 PCMCIA
	 * GPIO208 Output LCD_LED_ENABLE
	 * GPIO209 n/a pulled low
	 * GPIO210 n/a pulled low
	 * GPIO211 IrDA
	 * GPIO212 UART0
	 * GPIO213 Output PANEL_ON
	 * GPIO214 Input PANEL_READY
	 * GPIO215 MAC0
	 */
	li		t0, AU1100_GPIO2_ADDR
	sw		zero, gpio2_enable(t0)
	li		t1, 0x1
	sw		t1, gpio2_enable(t0)
	li		t1, 0x210F000C
	sw		t1, gpio2_output(t0)
	li		t1, 0x210F
	sw		t1, gpio2_dir(t0)
	sync

	/*
	 * Establish CLOCKing
	 *
	 * FREQ5: unused
	 * FREQ4: unused
	 * FREQ3: unused
	 * FREQ2: USBH, USBD, IrDA
	 * FREQ1: LCD (not setup here)
	 * FREQ0: unused
	 */
	li		t0, AU1100_SYS_ADDR
	li		t1, (0<<22)|(1<<21)|(1<<20)
	sw		t1, sys_freqctrl0(t0)
	li		t1, (4<<2)|(0<<1)|(0<<0)
	sw		t1, sys_clksrc(t0)
	sync
	
	sync
	jr		ra
	nop

/********************************************************************/

alldone:

	/*
	 * Prepare to invoke application main()
	 */
	.set reorder

/********************************************************************/