reset_pb1500.s

MIPS下的boottloader yamon 的源代码

	/* RCE1 */
	li		t1, MEM_STCFG1
	sw		t1, mem_stcfg1(t0)
	li		t1, MEM_STTIME1
	sw		t1, mem_sttime1(t0)
	li		t1, MEM_STADDR1
	sw		t1, mem_staddr1(t0)

	/* RCE2 */
	li		t1, MEM_STCFG2
	sw		t1, mem_stcfg2(t0)
	li		t1, MEM_STTIME2
	sw		t1, mem_sttime2(t0)
	li		t1, MEM_STADDR2
	sw		t1, mem_staddr2(t0)

	/* RCE3 */
	li		t1, MEM_STCFG3
	sw		t1, mem_stcfg3(t0)
	li		t1, MEM_STTIME3
	sw		t1, mem_sttime3(t0)
	li		t1, MEM_STADDR3
	sw		t1, mem_staddr3(t0)

	sync

	/*
	 * Step 15) Set peripherals to a known state
	 */
	li		t0, AU1500_IC0_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li		t0, AU1500_IC1_ADDR
	li		t1, 0xFFFFFFFF
	sw		t1, ic_cfg0clr(t0)
	sw		t1, ic_cfg1clr(t0)
	sw		t1, ic_cfg2clr(t0)
	sw		t1, ic_srcset(t0)
	sw		t1, ic_assignset(t0)
	sw		t1, ic_wakeclr(t0)
	sw		t1, ic_maskclr(t0)
	sw		t1, ic_risingclr(t0)
	sw		t1, ic_fallingclr(t0)
	sw		zero, ic_testbit(t0)
	sync

	li		t0, AU1500_SYS_ADDR
	sw		zero, sys_freqctrl0(t0)
	sw		zero, sys_freqctrl1(t0)
	sw		zero, sys_clksrc(t0)
	sw		zero, sys_pininputen(t0)
	sync

	li		t0, AU1500_AC97_ADDR
	li		t1, 0x2
	sw		t1, ac97_enable(t0)
	sync

	li		t0, AU1500_USBH_ADDR
	li		t1, usbh_enable
	addu	t0, t1, t0
	sw		zero, 0(t0)
	sync

	li		t0, AU1500_USBD_ADDR
	sw		zero, usbd_enable(t0)
	sync

	li		t0, AU1500_MACEN_ADDR
	sw		zero, macen_mac0(t0)
	sw		zero, macen_mac1(t0)
	sync

	li		t0, AU1500_UART0_ADDR
	sw		zero, uart_enable(t0)
	sync

	li		t0, AU1500_UART3_ADDR
	sw		zero, uart_enable(t0)
	sync


	/*
	 * Step 16) Determine cause of reset
	 */
	/* wait 10mS to debounce external signals */
	li		t1, MEM_1MS*10
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1500_SYS_ADDR
	lw		t1, sys_wakesrc(t0)

	/* Clear sys_wakemsk to prevent false events */
	sw		zero, sys_wakemsk(t0)
	sync

	/* Clear sys_wakesrc */
	//sw		zero, sys_wakesrc(t0)
	sync

	/* Check for Hardware Reset */
	andi	t2, t1, 0x01
	bne		zero, t2, hardwarereset

	/* Check for Sleep Wakeup */
	andi	t2, t1, 0x02
	bne		zero, t2, sleepwakeup
	nop

	/* Assume run-time reset */
	beq		zero, zero, runtimereset
	nop

/********************************************************************/

hardwarereset:

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal		initSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD
	 */
	bal		initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	beq		zero, zero, alldone
	nop

/********************************************************************/

runtimereset:

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal		initSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD
	 */
	bal		initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	beq		zero, zero, alldone
	nop

/********************************************************************/

sleepwakeup:

	/*
	 * Step 1) Initialize SDRAM. The SDRAM must be in self-refresh mode.
	 */
	bal		wakeupSDRAM
	nop

	/*
	 * Step 2) Initialize BOARD
	 */
	bal		initBOARD
	nop

	/*
	 * Step 3) Invoke application
	 */
	la		t0, AU1500_SYS_ADDR
	lw		sp, sys_scratch0(t0)
	lw		ra, sys_scratch1(t0)

	jr		ra
	nop

/********************************************************************/

	/*
	 * This routine initializes the SDRAM controller from Initial
	 * Power-up Reset or Running Reset.
	 */
initSDRAM:

	/* Only perform SDRAM init if running from ROM/Flash */
	addu	t2, ra, zero	/* preserve ra */
    bal		getPC
    nop
getPC:
    lui		t0, 0x1F00      /* ROM/flash address? */
    and		t1, t0, ra
	addu	ra, t2, zero	/* restore ra */
    bne		t0, t1, initSDRAMdone
    nop

	/* wait 1mS before setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1500_MEM_ADDR
	li		t1, MEM_SDMODE0
	sw		t1, mem_sdmode0(t0)

	li		t1, MEM_SDMODE1
	sw		t1, mem_sdmode1(t0)

	li		t1, MEM_SDMODE2
	sw		t1, mem_sdmode2(t0)
	
	li		t1, MEM_SDADDR0
	sw		t1, mem_sdaddr0(t0)

	li		t1, MEM_SDADDR1
	sw		t1, mem_sdaddr1(t0)

	li		t1, MEM_SDADDR2
	sw		t1, mem_sdaddr2(t0)

	sync

	li		t1, MEM_SDREFCFG_D
	sw		t1, mem_sdrefcfg(t0)
	sync

	sw		zero, mem_sdprecmd(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	li		t1, MEM_SDREFCFG_E
	sw		t1, mem_sdrefcfg(t0)
	sync

	li		t1, MEM_SDWRMD0
	sw		t1, mem_sdwrmd0(t0)		
	sync

	li		t1, MEM_SDWRMD1
	sw		t1, mem_sdwrmd1(t0)		
	sync

	li		t1, MEM_SDWRMD2
	sw		t1, mem_sdwrmd2(t0)
	sync

	/* wait 1mS after setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

initSDRAMdone:
	jr		ra
	nop

/********************************************************************/

wakeupSDRAM:

	li		t0, AU1500_MEM_ADDR

	li		t1, MEM_SDMODE0
	sw		t1, mem_sdmode0(t0)

	li		t1, MEM_SDMODE1
	sw		t1, mem_sdmode1(t0)

	li		t1, MEM_SDMODE2
	sw		t1, mem_sdmode2(t0)
	
	li		t1, MEM_SDADDR0
	sw		t1, mem_sdaddr0(t0)

	li		t1, MEM_SDADDR1
	sw		t1, mem_sdaddr1(t0)

	li		t1, MEM_SDADDR2
	sw		t1, mem_sdaddr2(t0)

	/*
	 * Issue 80ns of NOPs
	 * Must use non-cached KSEG1 address of Flash
	 */
	li		t1, 0xBFC00000
	lw		t1, 0(t1)
	sync
	
	/*
	 * Perform burst refresh of 4096 rows
	 */
	li		t1, 4096
burstrefresh:
	sw		zero, mem_sdautoref(t0)
	bne		zero, t1, burstrefresh
	addi	t1, t1, -1

	li		t1, MEM_SDREFCFG_E
	sw		t1, mem_sdrefcfg(t0)

	sync
	jr		ra
	nop

/********************************************************************/

initBOARD:

	/*
	 * External and/or board-specific peripheral initialization
	 */
#define PB1500_BCSR_ADDR 0xAE000000

	/*
	 * Establish MUXed pin functionality
	 *
	 *  CS=0
	 * USB=1 USBH
	 *  U3=0 UART3
	 * SRC=0 GPIO6
	 * EX1=0 GPIO3
	 * EX0=0 GPIO2
	 * UR3=1 UART3
	 * NI2=0 MAC1
	 *  U0=0 UART0
	 */
	li		t0, AU1500_SYS_ADDR
	li		t1,(1<<15)|(1<<7)
	sw		t1, sys_pinfunc(t0)

	/*
	 * Establish GPIO direction
	 *
	 * GPIO0 Input User defined
	 * GPIO1 Input User defined
	 * GPIO2 Input User defined
	 * GPIO3 Input User defined
	 * GPIO4 Input User defined
	 * GPIO5 Input User defined
	 * GPIO6 Input Switch S22
	 * GPIO7 Input User defined
	 * GPIO9 Input User defined
	 * GPIO10 Input User defined
	 * GPIO11 Input User defined
	 * GPIO12 Input User defined
	 * GPIO13 Input User defined
	 * GPIO14 Input User defined
	 * GPIO15 Input User defined
	 */
	li		t1,0x0000FFFF
	sw		t1, sys_trioutclr(t0)
	li		t1, 0x00000000
	sw		t1, sys_outputclr(t0)
	sync

	/*
	 * Establish GPIO2 direction
	 *
	 * GPIO200 Input Can be PCI_RST#
	 * GPIO201 Input PCMCIA Card Insert#
	 * GPIO202 Input PCMCIA Card STSCHG#
	 * GPIO203 Input PCMCIA Card IRQ#
	 * GPIO204 Input RTC IRQ#
	 * GPIO205 Input Daughtercard IRQ#
	 * GPIO206 Input 2-wire (not setup here)
	 * GPIO207 Input 2-wire (not setup here)
	 * GPIO208 Input GPIO HEX
	 * GPIO209 Input GPIO HEX
	 * GPIO210 Input GPIO HEX
	 * GPIO211 Input GPIO HEX
	 * GPIO212 Input YAMON endian
	 * GPIO213 Input
	 * GPIO214 Output LED D9
	 * GPIO215 Output LED D8
	 */
	li		t0, AU1500_GPIO2_ADDR
	li		t1,3
	sw		t1,gpio2_enable(t0)
	sync
	li		t1,1
	sw		t1,gpio2_enable(t0)
	sync
	sw		zero,gpio2_inten(t0)
	sync
	li		t1,(1<<15)|(1<<14)
	sw		t1,gpio2_dir(t0)
	sync
	li		t1,(1<<31)|(1<<30)|(0<<15)|(0<<14)
	sw		t1,gpio2_output(t0)
	sync

	/*
	 * Establish CLOCKing
	 *
	 * FREQ5: unused
	 * FREQ4: unused
	 * FREQ3: unused
	 * FREQ2: unused
	 * FREQ1: USBH and USBD (48MHz from AUXPLL)
	 * FREQ0: unused
	 */
	li		t0, AU1500_SYS_ADDR
	li		t1, (0<<12)|(1<<11)|(1<<10)
	sw		t1, sys_freqctrl0(t0)
	li		t1, (3<<12)|(0<<11)|(0<<10)|(3<<7)|(0<<6)|(0<<5)
	sw		t1, sys_clksrc(t0)
	sync

	/* Setup PCI Host - See Au1500 PCI app note */
	/* Enable PCI Clock - On Pb1500 PCI clock is external and always running */
	/* De-assert PCI_RST# - On Pb1500 PCI_RST# is handled externally by default */
	/* Wait 6 PCI clock cycles - On Pb1500 the bootup time meets this criteria */
	li		t0, AU1500_PCI_ADDR
	li		t1, 0x00000000
	sw		t1, pci_cmem(t0)
	li		t1, 0x0008000F
	sw		t1, pci_config(t0)
	li		t1, 0xFFFF0000
	sw		t1, pci_b2bmask_cch(t0)
	li		t1, 0x00000000
	sw		t1, pci_b2bbase0_venid(t0)
	li		t1, 0x00000000
	sw		t1, pci_b2bbase1_id(t0)
	li		t1, 0xE0000000
	sw		t1, pci_mwmask_dev(t0)
	li		t1, 0x00000000
	sw		t1, pci_mwbase_rev_ccl(t0)
	li		t1, 0x02A00356
	sw		t1, pci_statcmd(t0)
	li		t1, 0x00000000
	sw		t1, pci_hdrtype(t0)
	li		t1, 0x00000008
	sw		t1, pci_mbar(t0)
	li		t1, 0x00000000
	sw		t1, pci_timeout(t0)

	/* Take LSI PHYs out of reset */
	li		t0, PB1500_BCSR_ADDR
	li		t1, 3
	sw		t1, 0x0C(t0)

	/* Take SED13806 out of reset */
	li		t1, 0x80
	sw		t1, 0x14(t0)

	/* Ensure PCMCIA interface disabled */
	lw		t1, 0x10(t0)
	andi	t1,t1,0xFF00
	sw		t1, 0x10(t0)

	/* Enable DS1693 RTC, clear-out any wakeup events */
	li		t0, 0xAC000000
	lw		t1, 0x28(t0)	/* 0x0A << 2 */
	andi	t1, t1, 0x0F
	ori		t1, t1, 0x30	/* enable, select alternate bank */
	sw		t1, 0x28(t0)
	sync

	lw		t1, 0x12C(t0)	/* 0x4B << 2 */
	andi	t1, t1, 0xFC	/* clear KSE, WIE */
	sw		t1, 0x12C(t0)
	sync

	lw		t1, 0x128(t0)	/* 0x4A << 2 */
	ori		t1, t1, 0x08	/* set PAB */
	sw		t1, 0x128(t0)
	sync

	jr		ra
	nop

/********************************************************************/

alldone:

	/*
	 * Prepare to invoke application main()
	 */
	.set reorder

/********************************************************************/