reset_hydrogen.s

MIPS下的boottloader yamon 的源代码

	 * Step 11) Establish system bus divider
	 */
	li		t1, SYS_POWERCTRL
	sw		t1, sys_powerctrl(t0)
	sync

	/*
	 * Step 12) Establish AUX PLL frequency
	 */
	li		t1, SYS_AUXPLL
	sw		t1, sys_auxpll(t0)
	sync

	/*
	 * Step 13) Start the 32kHz oscillator
	 */
	li		t1, 0x00000100
	sw		t1, sys_cntctrl(t0)
	sync

	/*
	 * Step 14) Initialize static memory controller
	 */
	li		t0, AU1000_MEM_ADDR

	/* RCE0 */
	li		t1, MEM_STCFG0
	sw		t1, mem_stcfg0(t0)

	li		t1, MEM_STTIME0
	sw		t1, mem_sttime0(t0)

	li		t1, MEM_STADDR0
	sw		t1, mem_staddr0(t0)

	/* RCE1 */
	li		t1, MEM_STCFG1
	sw		t1, mem_stcfg1(t0)

	li		t1, MEM_STTIME1
	sw		t1, mem_sttime1(t0)

	li		t1, MEM_STADDR1
	sw		t1, mem_staddr1(t0)

	/* RCE2 */
	li		t1, MEM_STCFG2
	sw		t1, mem_stcfg2(t0)

	li		t1, MEM_STTIME2
	sw		t1, mem_sttime2(t0)

	li		t1, MEM_STADDR2
	sw		t1, mem_staddr2(t0)

	/* RCE3 */
	li		t1, MEM_STCFG3
	sw		t1, mem_stcfg3(t0)

	li		t1, MEM_STTIME3
	sw		t1, mem_sttime3(t0)

	li		t1, MEM_STADDR3
	sw		t1, mem_staddr3(t0)

	sync

	/*
	 * Step 15) Set peripherals to a known state
	 */
	li		t0, AU1000_SYS_ADDR
	sw		zero, sys_freqctrl0(t0)
	sw		zero, sys_freqctrl1(t0)
	sw		zero, sys_clksrc(t0)
	sw		zero, sys_pininputen(t0)
	sync

	li		t0, AU1000_AC97_ADDR
	li		t1, 0x2
	sw		t1, ac97_enable(t0)
	sync

	li		t0, AU1000_USBH_ADDR
	li		t1, usbh_enable
	addu	t0, t1, t0
	sw		zero, 0(t0)
	sync

	li		t0, AU1000_USBD_ADDR
	sw		zero, usbd_enable(t0)
	sync

	li		t0, AU1000_IRDA_ADDR
	sw		zero, irda_enable(t0)
	sync

	li		t0, AU1000_MACEN_ADDR
	sw		zero, macen_mac0(t0)
	sw		zero, macen_mac1(t0)
	sync

	li		t0, AU1000_I2S_ADDR
	li		t1, 0x02
	sw		t1, i2s_enable(t0)

	li		t0, AU1000_UART0_ADDR
	sw		zero, uart_enable(t0)
	sync

	li		t0, AU1000_UART1_ADDR
	sw		zero, uart_enable(t0)
	sync

	li		t0, AU1000_UART2_ADDR
	sw		zero, uart_enable(t0)
	sync

	li		t0, AU1000_UART3_ADDR
	sw		zero, uart_enable(t0)
	sync

	li		t0, AU1000_SSI0_ADDR
	li		t1, 0x02
	sw		t1, ssi_enable(t0)
	sync

	li		t0, AU1000_SSI1_ADDR
	li		t1, 0x02
	sw		t1, ssi_enable(t0)
	sync

	/*
	 * Step 16) Determine cause of reset
	 */
	/* wait 10mS to debounce external signals */
	li		t1, MEM_1MS*10
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1000_SYS_ADDR
	lw		t1, sys_wakesrc(t0)

	/* Clear sys_wakesrc */
	//sw		zero, sys_wakesrc(t0)
	sync

	/* Check for Hardware Reset */
	andi	t2, t1, 0x01
	bne		zero, t2, hardwarereset

	/* Check for Sleep Wakeup */
	andi	t2, t1, 0x02
	bne		zero, t2, sleepwakeup
	nop

	/* Assume run-time reset */
	beq		zero, zero, runtimereset
	nop

/********************************************************************/

hardwarereset:

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal		initSDRAM
	nop

	/*
	 * Step 2) Invoke application
	 */
	beq		zero, zero, alldone
	nop


/********************************************************************/

runtimereset:

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal		initSDRAM
	nop

	/*
	 * Step 2) Invoke application
	 */
	beq		zero, zero, alldone
	nop


/********************************************************************/

sleepwakeup:

#if 0
	/*
	 * Step 1) Initialize SDRAM. The SDRAM must be in self-refresh mode.
	 */
	bal		wakeupSDRAM	
	nop

	/*
	 * Step 2) Invoke application
	 */
	la		t0, AU1000_SYS_ADDR
	lw		sp, sys_scratch0(t0)
	lw		ra, sys_scratch1(t0)

	jr		ra
	nop

#else

	/*
	 * Step 1) Initialize SDRAM
	 */
	bal		initSDRAM
	nop 

	/*
	 * Step 2) Invoke application
	 */
	beq		zero, zero, alldone
	nop
#endif


/********************************************************************/

	/*
	 * This routine initializes the SDRAM controller from Initial
	 * Power-up Reset or Running Reset.
	 */
initSDRAM:

	/* Only perform SDRAM init if running from ROM/Flash */
	addu	t2, ra, zero	/* preserve ra */
    bal		getPC

    nop

getPC:

    lui		t0, 0x1F00      /* ROM/flash address? */

    and		t1, t0, ra

	addu	ra, t2, zero	/* restore ra */

    bne		t0, t1, initSDRAMdone

    nop

	/* wait 1mS before setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1000_MEM_ADDR
	li		t1, MEM_SDMODE0
	sw		t1, mem_sdmode0(t0)

	li		t1, MEM_SDMODE1
	sw		t1, mem_sdmode1(t0)

	li		t1, MEM_SDMODE2
	sw		t1, mem_sdmode2(t0)
	
	li		t1, MEM_SDADDR0
	sw		t1, mem_sdaddr0(t0)

	li		t1, MEM_SDADDR1
	sw		t1, mem_sdaddr1(t0)

	li		t1, MEM_SDADDR2
	sw		t1, mem_sdaddr2(t0)

	sync

	li		t1, MEM_SDREFCFG_D
	sw		t1, mem_sdrefcfg(t0)
	sync

	sw		zero, mem_sdprecmd(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	sw		zero, mem_sdautoref(t0)
	sync

	li		t1, MEM_SDREFCFG_E
	sw		t1, mem_sdrefcfg(t0)
	sync

	li		t1, MEM_SDWRMD0
	sw		t1, mem_sdwrmd0(t0)		
	sync

	
	/* wait 1mS after setup */
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

initSDRAMdone:
	jr		ra
	nop

/********************************************************************/

wakeupSDRAM:

	/*
	 * With SDRAM in self refresh mode, update the
	 * ADDR, MODE and refresh registers
	 */
	li		t0, AU1000_MEM_ADDR

	li		t1, MEM_SDMODE0
	sw		t1, mem_sdmode0(t0)

	li		t1, MEM_SDMODE1
	sw		t1, mem_sdmode1(t0)

	li		t1, MEM_SDMODE2
	sw		t1, mem_sdmode2(t0)
	
	li		t1, MEM_SDADDR0
	sw		t1, mem_sdaddr0(t0)

	li		t1, MEM_SDADDR1
	sw		t1, mem_sdaddr1(t0)

	li		t1, MEM_SDADDR2
	sw		t1, mem_sdaddr2(t0)

	sw		zero, mem_sdautoref(t0)

	li		t1, MEM_SDREFCFG_E
	sw		t1, mem_sdrefcfg(t0)

	sync

	jr		ra
	nop


/********************************************************************/

alldone:
	/*
	 * External and/or board-specific peripheral initialization
	 */


	/*
	 * Prepare to invoke application main()
	 */
	.set reorder

/********************************************************************/