📄 archdefs.h
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/*
* Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved.
*
* Unpublished rights reserved under the Copyright Laws of the United States of
* America.
*
* This document contains information that is proprietary to MIPS Technologies,
* Inc. ("MIPS Technologies"). Any copying, modifying or use of this information
* (in whole or in part) which is not expressly permitted in writing by MIPS
* Technologies or a contractually-authorized third party is strictly
* prohibited. At a minimum, this information is protected under unfair
* competition laws and the expression of the information contained herein is
* protected under federal copyright laws. Violations thereof may result in
* criminal penalties and fines.
* MIPS Technologies or any contractually-authorized third party reserves the
* right to change the information contained in this document to improve
* function, design or otherwise. MIPS Technologies does not assume any
* liability arising out of the application or use of this information. Any
* license under patent rights or any other intellectual property rights owned
* by MIPS Technologies or third parties shall be conveyed by MIPS Technologies
* or any contractually-authorized third party in a separate license agreement
* between the parties.
* The information contained in this document constitutes one or more of the
* following: commercial computer software, commercial computer software
* documentation or other commercial items. If the user of this information, or
* any related documentation of any kind, including related technical data or
* manuals, is an agency, department, or other entity of the United States
* government ("Government"), the use, duplication, reproduction, release,
* modification, disclosure, or transfer of this information, or any related
* documentation of any kind, is restricted in accordance with Federal
* Acquisition Regulation 12.212 for civilian agencies and Defense Federal
* Acquisition Regulation Supplement 227.7202 for military agencies. The use of
* this information by the Government is further restricted in accordance with
* the terms of the license agreement(s) and/or applicable contract terms and
* conditions covering this information from MIPS Technologies or any
* contractually-authorized third party.
*
*++
* File: ArchDefs.h
*
* Description:
* Architecture definitions
*
* Compile Options:
* MIPSAVPENV selects the special MIPS AVP environment
*
* Notes:
*
*
*/
#ifndef _ArchDefs_h_
#define _ArchDefs_h_
/*
* Utility defines for cross platform handling of 64bit constants.
*/
#if !defined(Append)
#define Append(c,s) (c##s)
#endif
#if !defined(__assembler) && !defined(MIPSAVPENV)
#if defined(NT)
#if !defined(UNS64Const)
#define UNS64Const(c) Append(c,ui64)
#endif
#if !defined(INT64Const)
#define INT64Const(c) Append(c,i64)
#endif
#else
#if !defined(UNS64Const)
#define UNS64Const(c) Append(c,ull)
#endif
#if !defined(INT64Const)
#define INT64Const(c) Append(c,ll)
#endif
#endif
#else /* Not C or C++ */
#if !defined(UNS64Const)
#define UNS64Const(c) c
#endif
#if !defined(INT64Const)
#define INT64Const(c) c
#endif
#endif /* C or C++ */
/*
************************************************************************
* I N S T R U C T I O N F O R M A T S *
************************************************************************
*
* The following definitions describe each field in an instruction. There
* is one diagram for each type of instruction, with field definitions
* following the diagram for that instruction. Note that if a field of
* the same name and position is defined in an earlier diagram, it is
* not defined again in the subsequent diagram. Only new fields are
* defined for each diagram.
*
* R-Type (operate)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | rs | rt | rd | sa | |
* | Opcode | | | Tcode | func |
* | | Bcode | | sel |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnOpcode 26
#define M_InstnOpcode (0x3f << S_InstnOpcode)
#define S_InstnRS 21
#define M_InstnRS (0x1f << S_InstnRS)
#define S_InstnRT 16
#define M_InstnRT (0x1f << S_InstnRT)
#define S_InstnRD 11
#define M_InstnRD (0x1f << S_InstnRD)
#define S_InstnSA 6
#define M_InstnSA (0x1f << S_InstnSA)
#define S_InstnTcode 6
#define M_InstnTcode (0x3ff << S_InstnTcode)
#define S_InstnBcode 6
#define M_InstnBcode (0xfffff << S_InstnBcode)
#define S_InstnFunc 0
#define M_InstnFunc (0x3f << S_InstnFunc)
#define S_InstnSel 0
#define M_InstnSel (0x7 << S_InstnSel)
/*
* I-Type (load, store, branch, immediate)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | rt | Offset |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnOffset 0
#define M_InstnOffset (0xffff << S_InstnOffset)
/*
* I-Type (pref)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | hint | Offset |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnHint S_InstnRT
#define M_InstnHint M_InstnRT
/*
* J-Type (jump)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | JIndex |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnJIndex 0
#define M_InstnJIndex (0x03ffffff << S_InstnJIndex)
/*
* FP R-Type (operate)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fmt | ft | fs | fd | func |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnFmt S_InstnRS
#define M_InstnFmt M_InstnRS
#define S_InstnFT S_InstnRT
#define M_InstnFT M_InstnRT
#define S_InstnFS S_InstnRD
#define M_InstnFS M_InstnRD
#define S_InstnFD S_InstnSA
#define M_InstnFD M_InstnSA
/*
* FP R-Type (cpu <-> cpu data movement))
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | sub | rt | fs | 0 |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnSub S_InstnRS
#define M_InstnSub M_InstnRS
/*
* FP R-Type (compare)
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | | | | | |C| |
* | Opcode | fmt | ft | fs | cc |0|A| func |
* | | | | | | |B| |
* | | | | | | |S| |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnCCcmp 8
#define M_InstnCCcmp (0x7 << S_InstnCCcmp)
#define S_InstnCABS 6
#define M_InstnCABS (0x1 << S_InstnCABS)
/*
* FP R-Type (FPR conditional move on FP cc)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fmt | cc |n|t| fs | fd | func |
* | | | |d|f| | | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnCC 18
#define M_InstnCC (0x7 << S_InstnCC)
#define S_InstnND 17
#define M_InstnND (0x1 << S_InstnND)
#define S_InstnTF 16
#define M_InstnTF (0x1 << S_InstnTF)
/*
* FP R-Type (3-operand operate)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fr | ft | fs | fd | op4 | fmt3|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnFR S_InstnRS
#define M_InstnFR M_InstnRS
#define S_InstnOp4 3
#define M_InstnOp4 (0x7 << S_InstnOp4)
#define S_InstnFmt3 0
#define M_InstnFmt3 (0x7 << S_InstnFmt3)
/*
* FP R-Type (Indexed load, store)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | rt | 0 | fd | func |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* FP R-Type (prefx)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | rt | hint | 0 | func |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnHintX S_InstnRD
#define M_InstnHintX M_InstnRD
/*
* FP R-Type (GPR conditional move on FP cc)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | cc |n|t| rd | 0 | func |
* | | | |d|f| | | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* FP I-Type (load, store)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | ft | Offset |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* FP I-Type (branch)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fmt | cc |n|t| Offset |
* | | | |d|f| |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
*************************************************************************
* V I R T U A L A D D R E S S D E F I N I T I O N S *
*************************************************************************
*/
#ifdef MIPSADDR64
#define A_K0BASE UNS64Const(0xffffffff80000000)
#define A_K1BASE UNS64Const(0xffffffffa0000000)
#define A_K2BASE UNS64Const(0xffffffffc0000000)
#define A_K3BASE UNS64Const(0xffffffffe0000000)
#define A_REGION UNS64Const(0xc000000000000000)
#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000)
#else
#define A_K0BASE 0x80000000
#define A_K1BASE 0xa0000000
#define A_K2BASE 0xc0000000
#define A_K3BASE 0xe0000000
#endif
#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */
#ifdef MIPS_Model64
#define S_VMAP64 62
#define M_VMAP64 UNS64Const(0xc000000000000000)
#define K_VMode11 3
#define K_VMode10 2
#define K_VMode01 1
#define K_VMode00 0
#define S_KSEG3 29
#define M_KSEG3 (0x7 << S_KSEG3)
#define K_KSEG3 7
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