atlas.h

MIPS下的boottloader yamon 的源代码

#define ATLAS_SWVALUE_S13_SHF	    10
#define ATLAS_SWVALUE_S13_MSK	    (MSK(1) << ATLAS_SWVALUE_S13_SHF)
#define ATLAS_SWVALUE_S13_SET       ATLAS_SWVALUE_S13_MSK

/* bit 9: S12 */
#define ATLAS_SWVALUE_S12_SHF	    9
#define ATLAS_SWVALUE_S12_MSK	    (MSK(1) << ATLAS_SWVALUE_S12_SHF)
#define ATLAS_SWVALUE_S12_SET       ATLAS_SWVALUE_S12_MSK

/* bit 8: S11 */
#define ATLAS_SWVALUE_S11_SHF	    8
#define ATLAS_SWVALUE_S11_MSK	    (MSK(1) << ATLAS_SWVALUE_S11_SHF)
#define ATLAS_SWVALUE_S11_SET       ATLAS_SWVALUE_S11_MSK

/* bits 7:0: S2 */
#define ATLAS_SWVALUE_S2_SHF	    0
#define ATLAS_SWVALUE_S2_MSK	    (MSK(8) << ATLAS_SWVALUE_S2_SHF)


/******** reg: STATUS ********/

/* bit 4 : MFWR */
#define ATLAS_STATUS_MFWR_SHF	    4
#define ATLAS_STATUS_MFWR_MSK	    (MSK(1) << ATLAS_STATUS_MFWR_SHF)
#define ATLAS_STATUS_MFWR_SET        ATLAS_STATUS_MFWR_MSK

/* bit 3 : S54 */
#define ATLAS_STATUS_S54_SHF	    3
#define ATLAS_STATUS_S54_MSK	    (MSK(1) << ATLAS_STATUS_S54_SHF)
#define ATLAS_STATUS_S54_SET        ATLAS_STATUS_S54_MSK

/* bit 2 : S53 */
#define ATLAS_STATUS_S53_SHF	    2
#define ATLAS_STATUS_S53_MSK	    (MSK(1) << ATLAS_STATUS_S53_SHF)
#define ATLAS_STATUS_S53_SET        ATLAS_STATUS_S53_MSK

/* bit 1: BIGEND */
#define ATLAS_STATUS_BIGEND_SHF	    1
#define ATLAS_STATUS_BIGEND_MSK	    (MSK(1) << ATLAS_STATUS_BIGEND_SHF)
#define ATLAS_STATUS_BIGEND_SET     ATLAS_STATUS_BIGEND_MSK

/* bit 0: PCISYS */
#define ATLAS_STATUS_PCISYS_SHF	    0
#define ATLAS_STATUS_PCISYS_MSK	    (MSK(1) << ATLAS_STATUS_PCISYS_SHF)
#define ATLAS_STATUS_PCISYS_SET     ATLAS_STATUS_PCISYS_MSK


/******** reg: JMPRS ********/

/* bit 1: EELOCK */
#define ATLAS_JMPRS_EELOCK_SHF	    1
#define ATLAS_JMPRS_EELOCK_MSK	    (MSK(1) << ATLAS_JMPRS_EELOCK_SHF)
#define ATLAS_JMPRS_EELOCK_SET      ATLAS_JMPRS_EELOCK_MSK

/* bit 0: PCI33M */
#define ATLAS_JMPRS_PCI33M_SHF	    0
#define ATLAS_JMPRS_PCI33M_MSK	    (MSK(1) << ATLAS_JMPRS_PCI33M_SHF)
#define ATLAS_JMPRS_PCI33M_SET      ATLAS_JMPRS_PCI33M_MSK


/************************************************************************
 *  DISPLAYS: 
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define ATLAS_LEDGREEN              0x1F000400 /* LEDGREEN              */
#define ATLAS_LEDBAR                0x1F000408 /* LEDBAR                */
#define ATLAS_ASCIIWORD             0x1F000410 /* ASCIIWORD             */
#define ATLAS_ASCIIPOS0             0x1F000418 /* ASCIIPOS0             */
#define ATLAS_ASCIIPOS1             0x1F000420 /* ASCIIPOS1             */
#define ATLAS_ASCIIPOS2             0x1F000428 /* ASCIIPOS2             */
#define ATLAS_ASCIIPOS3             0x1F000430 /* ASCIIPOS3             */
#define ATLAS_ASCIIPOS4             0x1F000438 /* ASCIIPOS4             */
#define ATLAS_ASCIIPOS5             0x1F000440 /* ASCIIPOS5             */
#define ATLAS_ASCIIPOS6             0x1F000448 /* ASCIIPOS6             */
#define ATLAS_ASCIIPOS7             0x1F000450 /* ASCIIPOS7             */


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: LEDGREEN ********/

/* bits 0: ON */
#define ATLAS_LEDGREEN_ON_SHF	    0
#define ATLAS_LEDGREEN_ON_MSK	    (MSK(1) << ATLAS_LEDGREEN_ON_SHF)
#define ATLAS_LEDGREEN_ON_SET       ATLAS_LEDGREEN_ON_MSK



/************************************************************************
 *  RESET CONTROL: 
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define ATLAS_SOFTRES               0x1F000500 /* SOFTRES               */
#define ATLAS_BRKRES                0x1F000508 /* BRKRES                */

/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: SOFTRES ********/

/* bits 7:0: RESET */
#define ATLAS_SOFTRES_RESET_SHF	    0
#define ATLAS_SOFTRES_RESET_MSK	    (MSK(8) << ATLAS_SOFTRES_RESET_SHF)
#define ATLAS_SOFTRES_RESET_GORESET 0x42     /* magic value to reset    */    


/******** reg: BRKRES ********/

/* bits 7:0: WIDTH */
#define ATLAS_BRKRES_WIDTH_SHF	    0
#define ATLAS_BRKRES_WIDTH_MSK	    (MSK(8) << ATLAS_BRKRES_WIDTH_SHF)


/************************************************************************
 *  PSU STANDBY CONTROL: 
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define ATLAS_PSUSTBY               0x1F000600 /* PSUSTBY               */


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: PSUSTBY ********/

/* bits 7:0: STBY */
#define ATLAS_PSUSTBY_STBY_SHF	    0
#define ATLAS_PSUSTBY_STBY_MSK	    (MSK(8) << ATLAS_PSUSTBY_STBY_SHF)
#define ATLAS_PSUSTBY_STBY_GOSTBY   0x4D     /* magic value to go stby  */    


/************************************************************************
 *  SYSTEM FLASH WRITE PROTECT CONTROL: 
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define ATLAS_SFWCTRL               0x1F000700 /* SFWCTRL               */


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: SFWCTRL ********/

/* bits 7:0: WRENA */
#define ATLAS_SFWCTRL_WRENA_SHF	    0
#define ATLAS_SFWCTRL_WRENA_MSK	    (MSK(8) << ATLAS_SFWCTRL_WRENA_SHF)
#define ATLAS_SFWCTRL_WRENA_ENSFWRITE 0xC7   /* magic value to enable 
                                                write protect           */    


/************************************************************************
 *  RTC-device indirect register access: 
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define ATLAS_RTCADR                0x1F000800 /* RTCADR                */
#define ATLAS_RTCDAT                0x1F000808 /* RTCDAT                */


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: RTCADR ********/

/* bits 7:0: ADR */
#define ATLAS_RTCADR_ADR_SHF	    0
#define ATLAS_RTCADR_ADR_MSK	    (MSK(8) << ATLAS_RTCADR_ADR_SHF)


/******** reg: RTCDAT ********/

/* bits 7:0: DATA */
#define ATLAS_RTCDAT_DATA_SHF	    0
#define ATLAS_RTCDAT_DATA_MSK	    (MSK(8) << ATLAS_RTCDAT_DATA_SHF)


/************************************************************************
 *  General Purpose Input Output Pin Control: 
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define ATLAS_GPOUT                 0x1F000A00 /* GPOUT                 */
#define ATLAS_GPINP                 0x1F000A08 /* GPINP                 */


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: GPOUT ********/

/* bits 7:0: OUTVAL */
#define ATLAS_GPOUT_OUTVAL_SHF	    0
#define ATLAS_GPOUT_OUTVAL_MSK	    (MSK(8) << ATLAS_GPOUT_OUTVAL_SHF)


/******** reg: GPINP ********/

/* bits 7:0: INPVAL */
#define ATLAS_GPINP_INPVAL_SHF	    0
#define ATLAS_GPINP_INPVAL_MSK	    (MSK(8) << ATLAS_GPINP_INPVAL_SHF)



/************************************************************************
 *      PCI definitions
 ************************************************************************/

/* ADP bit used as IDSEL during configuration cycles */
#define ATLAS_IDSEL_21150	    25
#define ATLAS_IDSEL_SYM53C810A	    26
#define ATLAS_IDSEL_CORE	    27
#define ATLAS_IDSEL_CONNECTOR	    28
#define ATLAS_IDSEL_SAA9730	    29


/**** Interrupt lines for ATLAS devices (on interrupt controller) ****/

/* PCI INTA..D       */
#define ATLAS_INTLINE_PCIA	    15
#define ATLAS_INTLINE_PCIB	    16
#define ATLAS_INTLINE_PCIC	    17
#define ATLAS_INTLINE_PCID	    18
/* Compact PCI A..D  */
#define ATLAS_INTLINE_CPCIA	    8
#define ATLAS_INTLINE_CPCIB	    9
#define ATLAS_INTLINE_CPCIC	    10
#define ATLAS_INTLINE_CPCID	    11
/* Local PCI devices */
#define ATLAS_INTLINE_9730	    ATLAS_INTLINE_PCIB
#define ATLAS_INTLINE_SCSI	    ATLAS_INTLINE_PCIC
/* Other devices     */
#define ATLAS_INTLINE_64120         5

/**** CPU interrupt lines used by devices ****/
#define ATLAS_CPUINT_ICTA	    C0_STATUS_IM_HW0


/************************************************************************
 *      MISC definitions
 ************************************************************************/

/* Lowest possible frequency for cpu (used during init for conservative
 * setup of timing (e.g. SDRAM refresh)
 */
#define ATLAS_CPUFREQ_LOWEST_MHZ     2

/* PCI device numbers */
#define ATLAS_DEVNUM_SAA9730       PCI_IDSEL2DEVNUM(ATLAS_IDSEL_SAA9730)
#define ATLAS_DEVNUM_PCI_SLOT	   PCI_IDSEL2DEVNUM(ATLAS_IDSEL_CONNECTOR)

#endif /* #ifndef ATLAS_H */