sead.h

MIPS下的boottloader yamon 的源代码

/************************************************************************
 *
 *      sead.h
 *
 *      The 'SEAD' module defines the SEAD board specific
 *      address-MAP, registers, etc.
 *
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/

#ifndef SEAD_H
#define  SEAD_H

/************************************************************************
 *  Note: all addresses are physical !
 *  Must be mapped into kseg0 (system RAM) or kseg1 (registers, devices)
*************************************************************************/

/************************************************************************
 *  Include files
 ************************************************************************/

#include "sysdefs.h"


/************************************************************************
 ************************************************************************
 *  SEAD physical address MAP (512 MByte)
 ************************************************************************
 ************************************************************************/

#define  SEAD_SYSTEMRAM_BASE         	0x00000000 /* System RAM:     */
#define  SEAD_SYSTEMRAM_SIZE         	0x10000000 /*   256 MByte     */

#define  SEAD_RESERVED1_BASE         	0x10000000 /* Reserved:       */
#define  SEAD_RESERVED1_SIZE         	0x0B000000 /*   176 MByte     */

#define  SEAD_SD_BASE       	  	0x1B000000 /* SDRAM control:  */
#define  SEAD_SD_SIZE       	  	0x00100000 /*     1 MByte     */

#define  SEAD_GP_BASE              	0x1B100000 /* GPIO module:    */
#define  SEAD_GP_SIZE              	0x00100000 /*     1 MByte     */

#define  SEAD_PF_BASE                	0x1B200000 /* PF module:      */
#define  SEAD_PF_SIZE                	0x00100000 /*     1 MByte     */

#define  SEAD_RESERVED2_BASE         	0x1B300000 /* Reserved:       */
#define  SEAD_RESERVED2_SIZE         	0x00D00000 /*    13 MByte     */

#define  SEAD_SYSTEMFLASH_BASE       	0x1C000000 /* System Flash:   */
#define  SEAD_SYSTEMFLASH_SIZE       	0x01FC0000 /*  31.75 MByte    */

#define  SEAD_SYSTEMFLASH_SECTORSIZE 	0x00020000 /* Sect. = 128 KB  */
#define  SEAD_SYSTEMFLASH_BANKCOUNT   	         2 /*                 */
#define  SEAD_SYSTEMFLASH_BLOCKCOUNT   	        64 /*                 */


#define  SEAD_FILEFLASH_BASE         	0x1DFC0000 /* File Flash:     */
#define  SEAD_FILEFLASH_SIZE         	0x00040000 /*   256 KByte     */

#define  SEAD_FILEFLASH_SECTORSIZE   	0x00020000 /* Sect. = 128 KB  */

#define  SEAD_SRAM_BASE              	0x1E000000 /* System RAM:     */
#define  SEAD_SRAM_SIZE              	0x00400000 /*     4 MByte     */

#define  SEAD_RESERVED3_BASE         	0x1E400000 /* Reserved:       */
#define  SEAD_RESERVED3_SIZE         	0x00400000 /*     4 MByte     */

#define  SEAD_PI_BASE           	0x1E800000 /* PI-bus ctrl:    */
#define  SEAD_PI_SIZE           	0x00400000 /*     4 MByte     */

#define  SEAD_RESERVED4_BASE         	0x1EC00000 /* Reserved:       */
#define  SEAD_RESERVED4_SIZE         	0x00400000 /*     4 MByte     */

#define  SEAD_DEVICES_BASE           	0x1F000000 /* Devices:        */
#define  SEAD_DEVICES_SIZE           	0x00C00000 /*    12 MByte     */

#define  SEAD_BOOTPROM_BASE          	0x1FC00000 /* Boot PROM:      */
#define  SEAD_BOOTPROM_SIZE          	0x00100000 /*     1 MByte     */


/************************************************************************
 *  SEAD, peripheral bus devices, base adresses:
 ************************************************************************/

#define  SEAD_HDSP2532_BASE          	0x1F000400 /* ASCII display	*/
#define  SEAD_TI16C550_DEV0_BASE     	0x1F000800 /* TI16C550 UART0	*/
#define  SEAD_TI16C550_DEV1_BASE     	0x1F000900 /* TI16C550 UART1	*/


/************************************************************************
 ************************************************************************
 *  SEAD FPGA, PERIPHERAL REGISTERS:
 ************************************************************************
 ************************************************************************/

/************************************************************************
 *  REVISION: MUST BE FIXED TO  0x1FC00010 on any baseboard
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define SEAD_REVISION      	     	0x1FC00010 /* REVISION		*/


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: REVISION ********/

/* field: RTLID */
#define SEAD_REVISION_RTLID_SHF		26
#define SEAD_REVISION_RTLID_MSK		(MSK(6) << SEAD_REVISION_RTLID_SHF)
#define SEAD_REVISION_RTLID_BASIC	0x1

/* field: RTLMAJ */
#define SEAD_REVISION_RTLMAJ_SHF	19
#define SEAD_REVISION_RTLMAJ_MSK	(MSK(7) << SEAD_REVISION_RTLMAJ_SHF)

/* field: RTLMIN */
#define SEAD_REVISION_RTLMIN_SHF	12
#define SEAD_REVISION_RTLMIN_MSK	(MSK(7) << SEAD_REVISION_RTLMIN_SHF)

/* field: PROID */
#define SEAD_REVISION_PROID_SHF		4
#define SEAD_REVISION_PROID_MSK		(MSK(4) << SEAD_REVISION_PROID_SHF)

/* field: PRORV */
#define SEAD_REVISION_PRORV_SHF		0
#define SEAD_REVISION_PRORV_MSK		(MSK(4) << SEAD_REVISION_PRORV_SHF)


/************************************************************************
 *  PERIPHERAL BUS SWITCHES (P-SWITCH):
*************************************************************************/

/************************************************************************
 *      P-SW Register Addresses
*************************************************************************/

#define SEAD_PSWITCH		   	0x1F000200 /* P-SWITCH         	*/


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: PSWITCH ********/
/* bits 7:0: VAL */
#define SEAD_PSWITCH_VAL_SHF	    	0
#define SEAD_PSWITCH_VAL_MSK	    	(MSK(8) << SEAD_PSWITCH_VAL_SHF)


/* bit 0: S3-1 */
#define SEAD_PSWITCH_SW1_SHF	    	0
#define SEAD_PSWITCH_SW1_MSK	    	(MSK(1) << SEAD_PSWITCH_SW1_SHF)
#define SEAD_PSWITCH_SW1_ON           	SEAD_PSWITCH_SW1_MSK

/* bit 1: S3-2 */
#define SEAD_PSWITCH_SW2_SHF	    	1
#define SEAD_PSWITCH_SW2_MSK	    	(MSK(1) << SEAD_PSWITCH_SW2_SHF)
#define SEAD_PSWITCH_SW2_ON           	SEAD_PSWITCH_SW2_MSK

/* bit 2: S3-3 */
#define SEAD_PSWITCH_SW3_SHF	    	2
#define SEAD_PSWITCH_SW3_MSK	    	(MSK(1) << SEAD_PSWITCH_SW3_SHF)
#define SEAD_PSWITCH_SW3_ON           	SEAD_PSWITCH_SW3_MSK

/* bit 3: S3-4 */
#define SEAD_PSWITCH_SW4_SHF	    	3
#define SEAD_PSWITCH_SW4_MSK	    	(MSK(1) << SEAD_PSWITCH_SW4_SHF)
#define SEAD_PSWITCH_SW4_ON           	SEAD_PSWITCH_SW4_MSK

/* bit 4: S3-5 */
#define SEAD_PSWITCH_SW5_SHF	    	4
#define SEAD_PSWITCH_SW5_MSK	    	(MSK(1) << SEAD_PSWITCH_SW5_SHF)
#define SEAD_PSWITCH_SW5_ON           	SEAD_PSWITCH_SW5_MSK

/* bit 5: S3-6 */
#define SEAD_PSWITCH_SW6_SHF	    	5
#define SEAD_PSWITCH_SW6_MSK	    	(MSK(1) << SEAD_PSWITCH_SW6_SHF)
#define SEAD_PSWITCH_SW6_ON           	SEAD_PSWITCH_SW6_MSK

/* bit 6: S3-7 */
#define SEAD_PSWITCH_SW7_SHF	    	6
#define SEAD_PSWITCH_SW7_MSK	  	(MSK(1) << SEAD_PSWITCH_SW7_SHF)
#define SEAD_PSWITCH_SW7_ON           	SEAD_PSWITCH_SW7_MSK

/* bit 7: S3-8 */
#define SEAD_PSWITCH_SW8_SHF	    	7
#define SEAD_PSWITCH_SW8_MSK	  	(MSK(1) << SEAD_PSWITCH_SW8_SHF)
#define SEAD_PSWITCH_SW8_ON           	SEAD_PSWITCH_SW8_MSK


/************************************************************************
 *  PERIPHERAL BUS LEDs (P-LED):
*************************************************************************/

/************************************************************************
 *      P-LED Register Addresses
*************************************************************************/

#define SEAD_PLED		   	0x1F000210 /* P-LED         	*/


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: PLED ********/
/* bits 7:0: VAL */
#define SEAD_PLED_VAL_SHF	    	0
#define SEAD_PLED_VAL_MSK	    	(MSK(8) << SEAD_PLED_VAL_SHF)


/* bit 0:  */
#define SEAD_PLED_BIT0_SHF	    	0
#define SEAD_PLED_BIT0_MSK	    	(MSK(1) << SEAD_PLED_BIT0_SHF)
#define SEAD_PLED_BIT0_ON           	SEAD_PLED_BIT0_MSK

/* bit 1:  */
#define SEAD_PLED_BIT1_SHF	    	1
#define SEAD_PLED_BIT1_MSK	    	(MSK(1) << SEAD_PLED_BIT1_SHF)
#define SEAD_PLED_BIT1_ON           	SEAD_PLED_BIT1_MSK

/* bit 2:  */
#define SEAD_PLED_BIT2_SHF	    	2
#define SEAD_PLED_BIT2_MSK	    	(MSK(1) << SEAD_PLED_BIT2_SHF)
#define SEAD_PLED_BIT2_ON           	SEAD_PLED_BIT2_MSK

/* bit 3:  */
#define SEAD_PLED_BIT3_SHF	    	3
#define SEAD_PLED_BIT3_MSK	    	(MSK(1) << SEAD_PLED_BIT3_SHF)
#define SEAD_PLED_BIT3_ON           	SEAD_PLED_BIT3_MSK

/* bit 4:  */
#define SEAD_PLED_BIT4_SHF	    	4
#define SEAD_PLED_BIT4_MSK	    	(MSK(1) << SEAD_PLED_BIT4_SHF)
#define SEAD_PLED_BIT4_ON           	SEAD_PLED_BIT4_MSK

/* bit 5:  */
#define SEAD_PLED_BIT5_SHF	    	5
#define SEAD_PLED_BIT5_MSK	    	(MSK(1) << SEAD_PLED_BIT5_SHF)
#define SEAD_PLED_BIT5_ON           	SEAD_PLED_BIT5_MSK

/* bit 6:  */
#define SEAD_PLED_BIT6_SHF	    	6
#define SEAD_PLED_BIT6_MSK	    	(MSK(1) << SEAD_PLED_BIT6_SHF)
#define SEAD_PLED_BIT6_ON           	SEAD_PLED_BIT6_MSK

/* bit 7:  */
#define SEAD_PLED_BIT7_SHF	    	7
#define SEAD_PLED_BIT7_MSK	    	(MSK(1) << SEAD_PLED_BIT7_SHF)
#define SEAD_PLED_BIT7_ON           	SEAD_PLED_BIT7_MSK


/************************************************************************
 *  ASCII DISPLAY
*************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define SEAD_ASCIIPOS0          	0x1F0005C0
#define SEAD_ASCIIPOS1          	0x1F0005C8
#define SEAD_ASCIIPOS2          	0x1F0005D0
#define SEAD_ASCIIPOS3          	0x1F0005D8
#define SEAD_ASCIIPOS4          	0x1F0005E0
#define SEAD_ASCIIPOS5          	0x1F0005E8
#define SEAD_ASCIIPOS6          	0x1F0005F0
#define SEAD_ASCIIPOS7          	0x1F0005F8


/************************************************************************
 ************************************************************************
 *  SEAD FPGA, PERIPHERAL BUS CONTROLLER REGISTERS:
 ************************************************************************
 ************************************************************************/

/************************************************************************
 *      Register Addresses
*************************************************************************/

#define SEAD_PI_TIMSRAM             	(SEAD_PI_BASE + 0x0010)
#define SEAD_PI_TIMOTHER            	(SEAD_PI_BASE + 0x0020)


/************************************************************************
 *      Register field encodings
*************************************************************************/


/******** reg: PI_TIMSRAM ********/

/* bit 2:0 : */
#define SEAD_PI_TIMSRAM_CS1_SHF		0
#define SEAD_PI_TIMSRAM_CS1_MSK		(MSK(3) << SEAD_PI_TIMSRAM_CS1_SHF)

/* bit 7:3 : */
#define SEAD_PI_TIMSRAM_CS2_SHF		3
#define SEAD_PI_TIMSRAM_CS2_MSK		(MSK(5) << SEAD_PI_TIMSRAM_CS2_SHF)

/* bit 10:8 : */
#define SEAD_PI_TIMSRAM_RD1_SHF		8
#define SEAD_PI_TIMSRAM_RD1_MSK		(MSK(3) << SEAD_PI_TIMSRAM_RD1_SHF)

/* bit 16:11 : */
#define SEAD_PI_TIMSRAM_RD2_SHF		11
#define SEAD_PI_TIMSRAM_RD2_MSK		(MSK(6) << SEAD_PI_TIMSRAM_RD2_SHF)

/* bit 19:17 : */
#define SEAD_PI_TIMSRAM_WE1_SHF		17
#define SEAD_PI_TIMSRAM_WE1_MSK		(MSK(3) << SEAD_PI_TIMSRAM_WE1_SHF)

/* bit 25:20 : */
#define SEAD_PI_TIMSRAM_WE2_SHF		20
#define SEAD_PI_TIMSRAM_WE2_MSK		(MSK(6) << SEAD_PI_TIMSRAM_WE2_SHF)

/* bit 31:26 : */
#define SEAD_PI_TIMSRAM_ADH_SHF		26
#define SEAD_PI_TIMSRAM_ADH_MSK		(MSK(6) << SEAD_PI_TIMSRAM_ADH_SHF)


/******** reg: PI_TIMOTHER ********/

/* bit 2:0 : */
#define SEAD_PI_TIMOTHER_CS1_SHF	0
#define SEAD_PI_TIMOTHER_CS1_MSK	(MSK(3) << SEAD_PI_TIMOTHER_CS1_SHF)

/* bit 7:3 : */
#define SEAD_PI_TIMOTHER_CS2_SHF	3
#define SEAD_PI_TIMOTHER_CS2_MSK	(MSK(5) << SEAD_PI_TIMOTHER_CS2_SHF)

/* bit 10:8 : */
#define SEAD_PI_TIMOTHER_RD1_SHF	8
#define SEAD_PI_TIMOTHER_RD1_MSK	(MSK(3) << SEAD_PI_TIMOTHER_RD1_SHF)

/* bit 16:11 : */
#define SEAD_PI_TIMOTHER_RD2_SHF	11
#define SEAD_PI_TIMOTHER_RD2_MSK	(MSK(6) << SEAD_PI_TIMOTHER_RD2_SHF)

/* bit 19:17 : */
#define SEAD_PI_TIMOTHER_WE1_SHF	17
#define SEAD_PI_TIMOTHER_WE1_MSK	(MSK(3) << SEAD_PI_TIMOTHER_WE1_SHF)