icta.h

MIPS下的boottloader yamon 的源代码

/* bit 17: CONINTCN */
#define ICTA_INTRSTEN_CONINTCN_SHF	17
#define ICTA_INTRSTEN_CONINTCN_MSK	(MSK(1) << ICTA_INTRSTEN_CONINTCN_SHF)
#define ICTA_INTRSTEN_CONINTCN_SET	ICTA_INTRSTEN_CONINTCN_MSK

/* bit 16: CONINTBN */
#define ICTA_INTRSTEN_CONINTBN_SHF	16
#define ICTA_INTRSTEN_CONINTBN_MSK	(MSK(1) << ICTA_INTRSTEN_CONINTBN_SHF)
#define ICTA_INTRSTEN_CONINTBN_SET	ICTA_INTRSTEN_CONINTBN_MSK

/* bit 15: CONINTAN */
#define ICTA_INTRSTEN_CONINTAN_SHF	15
#define ICTA_INTRSTEN_CONINTAN_MSK	(MSK(1) << ICTA_INTRSTEN_CONINTAN_SHF)
#define ICTA_INTRSTEN_CONINTAN_SET	ICTA_INTRSTEN_CONINTAN_MSK

/* bit 14: ATXOKN */
#define ICTA_INTRSTEN_ATXOKN_SHF	14
#define ICTA_INTRSTEN_ATXOKN_MSK	(MSK(1) << ICTA_INTRSTEN_ATXOKN_SHF)
#define ICTA_INTRSTEN_ATXOKN_SET	ICTA_INTRSTEN_ATXOKN_MSK

/* bit 13: DEG */
#define ICTA_INTRSTEN_DEG_SHF	        13
#define ICTA_INTRSTEN_DEG_MSK	        (MSK(1) << ICTA_INTRSTEN_DEG_SHF)
#define ICTA_INTRSTEN_DEG_SET	        ICTA_INTRSTEN_DEG_MSK

/* bit 12: ENUM */
#define ICTA_INTRSTEN_ENUM_SHF	        12
#define ICTA_INTRSTEN_ENUM_MSK	        (MSK(1) << ICTA_INTRSTEN_ENUM_SHF)
#define ICTA_INTRSTEN_ENUM_SET	        ICTA_INTRSTEN_ENUM_MSK

/* bit 11: PCID */
#define ICTA_INTRSTEN_PCID_SHF	        11
#define ICTA_INTRSTEN_PCID_MSK	        (MSK(1) << ICTA_INTRSTEN_PCID_SHF)
#define ICTA_INTRSTEN_PCID_SET	        ICTA_INTRSTEN_PCID_MSK

/* bit 10: PCIC */
#define ICTA_INTRSTEN_PCIC_SHF	        10
#define ICTA_INTRSTEN_PCIC_MSK	        (MSK(1) << ICTA_INTRSTEN_PCIC_SHF)
#define ICTA_INTRSTEN_PCIC_SET	        ICTA_INTRSTEN_PCIC_MSK

/* bit 9: PCIB */
#define ICTA_INTRSTEN_PCIB_SHF	        9
#define ICTA_INTRSTEN_PCIB_MSK	        (MSK(1) << ICTA_INTRSTEN_PCIB_SHF)
#define ICTA_INTRSTEN_PCIB_SET	        ICTA_INTRSTEN_PCIB_MSK

/* bit 8: PCIA */
#define ICTA_INTRSTEN_PCIA_SHF	        8
#define ICTA_INTRSTEN_PCIA_MSK	        (MSK(1) << ICTA_INTRSTEN_PCIA_SHF)
#define ICTA_INTRSTEN_PCIA_SET	        ICTA_INTRSTEN_PCIA_MSK

/* bit 7: NMI */
#define ICTA_INTRSTEN_NMI_SHF	        7
#define ICTA_INTRSTEN_NMI_MSK	        (MSK(1) << ICTA_INTRSTEN_NMI_SHF)
#define ICTA_INTRSTEN_NMI_SET	        ICTA_INTRSTEN_NMI_MSK

/* bit 6: CORELO */
#define ICTA_INTRSTEN_CORELO_SHF	6
#define ICTA_INTRSTEN_CORELO_MSK	(MSK(1) << ICTA_INTRSTEN_CORELO_SHF)
#define ICTA_INTRSTEN_CORELO_SET	ICTA_INTRSTEN_CORELO_MSK

/* bit 5: COREHI */
#define ICTA_INTRSTEN_COREHI_SHF	5
#define ICTA_INTRSTEN_COREHI_MSK	(MSK(1) << ICTA_INTRSTEN_COREHI_SHF)
#define ICTA_INTRSTEN_COREHI_SET	ICTA_INTRSTEN_COREHI_MSK

/* bit 4: RTC */
#define ICTA_INTRSTEN_RTC_SHF	        4
#define ICTA_INTRSTEN_RTC_MSK	        (MSK(1) << ICTA_INTRSTEN_RTC_SHF)
#define ICTA_INTRSTEN_RTC_SET	        ICTA_INTRSTEN_RTC_MSK

/* bit 2: TIM1 */
#define ICTA_INTRSTEN_TIM1_SHF	        2
#define ICTA_INTRSTEN_TIM1_MSK	        (MSK(1) << ICTA_INTRSTEN_TIM1_SHF)
#define ICTA_INTRSTEN_TIM1_SET	        ICTA_INTRSTEN_TIM1_MSK

/* bit 1: TIM0 */
#define ICTA_INTRSTEN_TIM0_SHF	        1
#define ICTA_INTRSTEN_TIM0_MSK	        (MSK(1) << ICTA_INTRSTEN_TIM0_SHF)
#define ICTA_INTRSTEN_TIM0_SET	        ICTA_INTRSTEN_TIM0_MSK

/* bit 0: SER */
#define ICTA_INTRSTEN_SER_SHF	        0
#define ICTA_INTRSTEN_SER_MSK	        (MSK(1) << ICTA_INTRSTEN_SER_SHF)
#define ICTA_INTRSTEN_SER_SET	        ICTA_INTRSTEN_SER_MSK



/******** reg: INTENABLE ********/


/* bit 19: PCISERRN */
#define ICTA_INTENABLE_PCISERRN_SHF	19
#define ICTA_INTENABLE_PCISERRN_MSK	(MSK(1) << ICTA_INTENABLE_PCISERRN_SHF)
#define ICTA_INTENABLE_PCISERRN_SET	ICTA_INTENABLE_PCISERRN_MSK

/* bit 18: CONINTDN */
#define ICTA_INTENABLE_CONINTDN_SHF	18
#define ICTA_INTENABLE_CONINTDN_MSK	(MSK(1) << ICTA_INTENABLE_CONINTDN_SHF)
#define ICTA_INTENABLE_CONINTDN_SET	ICTA_INTENABLE_CONINTDN_MSK

/* bit 17: CONINTCN */
#define ICTA_INTENABLE_CONINTCN_SHF	17
#define ICTA_INTENABLE_CONINTCN_MSK	(MSK(1) << ICTA_INTENABLE_CONINTCN_SHF)
#define ICTA_INTENABLE_CONINTCN_SET	ICTA_INTENABLE_CONINTCN_MSK

/* bit 16: CONINTBN */
#define ICTA_INTENABLE_CONINTBN_SHF	16
#define ICTA_INTENABLE_CONINTBN_MSK	(MSK(1) << ICTA_INTENABLE_CONINTBN_SHF)
#define ICTA_INTENABLE_CONINTBN_SET	ICTA_INTENABLE_CONINTBN_MSK

/* bit 15: CONINTAN */
#define ICTA_INTENABLE_CONINTAN_SHF	15
#define ICTA_INTENABLE_CONINTAN_MSK	(MSK(1) << ICTA_INTENABLE_CONINTAN_SHF)
#define ICTA_INTENABLE_CONINTAN_SET	ICTA_INTENABLE_CONINTAN_MSK

/* bit 14: ATXOKN */
#define ICTA_INTENABLE_ATXOKN_SHF	14
#define ICTA_INTENABLE_ATXOKN_MSK	(MSK(1) << ICTA_INTENABLE_ATXOKN_SHF)
#define ICTA_INTENABLE_ATXOKN_SET       ICTA_INTENABLE_ATXOKN_MSK

/* bit 13: DEG */
#define ICTA_INTENABLE_DEG_SHF	        13
#define ICTA_INTENABLE_DEG_MSK	        (MSK(1) << ICTA_INTENABLE_DEG_SHF)
#define ICTA_INTENABLE_DEG_SET	        ICTA_INTENABLE_DEG_MSK

/* bit 12: ENUM */
#define ICTA_INTENABLE_ENUM_SHF	        12
#define ICTA_INTENABLE_ENUM_MSK	        (MSK(1) << ICTA_INTENABLE_ENUM_SHF)
#define ICTA_INTENABLE_ENUM_SET	        ICTA_INTENABLE_ENUM_MSK

/* bit 11: PCID */
#define ICTA_INTENABLE_PCID_SHF	        11
#define ICTA_INTENABLE_PCID_MSK	        (MSK(1) << ICTA_INTENABLE_PCID_SHF)
#define ICTA_INTENABLE_PCID_SET	        ICTA_INTENABLE_PCID_MSK

/* bit 10: PCIC */
#define ICTA_INTENABLE_PCIC_SHF	        10
#define ICTA_INTENABLE_PCIC_MSK	        (MSK(1) << ICTA_INTENABLE_PCIC_SHF)
#define ICTA_INTENABLE_PCIC_SET	        ICTA_INTENABLE_PCIC_MSK

/* bit 9: PCIB */
#define ICTA_INTENABLE_PCIB_SHF	        9
#define ICTA_INTENABLE_PCIB_MSK	        (MSK(1) << ICTA_INTENABLE_PCIB_SHF)
#define ICTA_INTENABLE_PCIB_SET	        ICTA_INTENABLE_PCIB_MSK

/* bit 8: PCIA */
#define ICTA_INTENABLE_PCIA_SHF	        8
#define ICTA_INTENABLE_PCIA_MSK	        (MSK(1) << ICTA_INTENABLE_PCIA_SHF)
#define ICTA_INTENABLE_PCIA_SET	        ICTA_INTENABLE_PCIA_MSK

/* bit 7: NMI */
#define ICTA_INTENABLE_NMI_SHF	        7
#define ICTA_INTENABLE_NMI_MSK	        (MSK(1) << ICTA_INTENABLE_NMI_SHF)
#define ICTA_INTENABLE_NMI_SET	        ICTA_INTENABLE_NMI_MSK

/* bit 6: CORELO */
#define ICTA_INTENABLE_CORELO_SHF	6
#define ICTA_INTENABLE_CORELO_MSK	(MSK(1) << ICTA_INTENABLE_CORELO_SHF)
#define ICTA_INTENABLE_CORELO_SET	ICTA_INTENABLE_CORELO_MSK

/* bit 5: COREHI */
#define ICTA_INTENABLE_COREHI_SHF	5
#define ICTA_INTENABLE_COREHI_MSK	(MSK(1) << ICTA_INTENABLE_COREHI_SHF)
#define ICTA_INTENABLE_COREHI_SET	ICTA_INTENABLE_COREHI_MSK

/* bit 4: RTC */
#define ICTA_INTENABLE_RTC_SHF	        4
#define ICTA_INTENABLE_RTC_MSK	        (MSK(1) << ICTA_INTENABLE_RTC_SHF)
#define ICTA_INTENABLE_RTC_SET	        ICTA_INTENABLE_RTC_MSK

/* bit 2: TIM1 */
#define ICTA_INTENABLE_TIM1_SHF	        2
#define ICTA_INTENABLE_TIM1_MSK	        (MSK(1) << ICTA_INTENABLE_TIM1_SHF)
#define ICTA_INTENABLE_TIM1_SET	        ICTA_INTENABLE_TIM1_MSK

/* bit 1: TIM0 */
#define ICTA_INTENABLE_TIM0_SHF	        1
#define ICTA_INTENABLE_TIM0_MSK	        (MSK(1) << ICTA_INTENABLE_TIM0_SHF)
#define ICTA_INTENABLE_TIM0_SET	        ICTA_INTENABLE_TIM0_MSK

/* bit 0: SER */
#define ICTA_INTENABLE_SER_SHF	        0
#define ICTA_INTENABLE_SER_MSK	        (MSK(1) << ICTA_INTENABLE_SER_SHF)
#define ICTA_INTENABLE_SER_SET	        ICTA_INTENABLE_SER_MSK



/******** reg: INTSTATUS ********/


/* bit 19: PCISERRN */
#define ICTA_INTSTATUS_PCISERRN_SHF	19
#define ICTA_INTSTATUS_PCISERRN_MSK	(MSK(1) << ICTA_INTSTATUS_PCISERRN_SHF)
#define ICTA_INTSTATUS_PCISERRN_SET	ICTA_INTSTATUS_PCISERRN_MSK

/* bit 18: CONINTDN */
#define ICTA_INTSTATUS_CONINTDN_SHF	18
#define ICTA_INTSTATUS_CONINTDN_MSK	(MSK(1) << ICTA_INTSTATUS_CONINTDN_SHF)
#define ICTA_INTSTATUS_CONINTDN_SET	ICTA_INTSTATUS_CONINTDN_MSK

/* bit 17: CONINTCN */
#define ICTA_INTSTATUS_CONINTCN_SHF	17
#define ICTA_INTSTATUS_CONINTCN_MSK	(MSK(1) << ICTA_INTSTATUS_CONINTCN_SHF)
#define ICTA_INTSTATUS_CONINTCN_SET	ICTA_INTSTATUS_CONINTCN_MSK

/* bit 16: CONINTBN */
#define ICTA_INTSTATUS_CONINTBN_SHF	16
#define ICTA_INTSTATUS_CONINTBN_MSK	(MSK(1) << ICTA_INTSTATUS_CONINTBN_SHF)
#define ICTA_INTSTATUS_CONINTBN_SET	ICTA_INTSTATUS_CONINTBN_MSK

/* bit 15: CONINTAN */
#define ICTA_INTSTATUS_CONINTAN_SHF	15
#define ICTA_INTSTATUS_CONINTAN_MSK	(MSK(1) << ICTA_INTSTATUS_CONINTAN_SHF)
#define ICTA_INTSTATUS_CONINTAN_SET	ICTA_INTSTATUS_CONINTAN_MSK

/* bit 14: ATXOKN */
#define ICTA_INTSTATUS_ATXOKN_SHF	14
#define ICTA_INTSTATUS_ATXOKN_MSK	(MSK(1) << ICTA_INTSTATUS_ATXOKN_SHF)
#define ICTA_INTSTATUS_ATXOKN_SET	ICTA_INTSTATUS_ATXOKN_MSK

/* bit 13: DEG */
#define ICTA_INTSTATUS_DEG_SHF	        13
#define ICTA_INTSTATUS_DEG_MSK	        (MSK(1) << ICTA_INTSTATUS_DEG_SHF)
#define ICTA_INTSTATUS_DEG_SET	        ICTA_INTSTATUS_DEG_MSK

/* bit 12: ENUM */
#define ICTA_INTSTATUS_ENUM_SHF	        12
#define ICTA_INTSTATUS_ENUM_MSK	        (MSK(1) << ICTA_INTSTATUS_ENUM_SHF)
#define ICTA_INTSTATUS_ENUM_SET	        ICTA_INTSTATUS_ENUM_MSK

/* bit 11: PCID */
#define ICTA_INTSTATUS_PCID_SHF	        11
#define ICTA_INTSTATUS_PCID_MSK	        (MSK(1) << ICTA_INTSTATUS_PCID_SHF)
#define ICTA_INTSTATUS_PCID_SET	        ICTA_INTSTATUS_PCID_MSK

/* bit 10: PCIC */
#define ICTA_INTSTATUS_PCIC_SHF	        10
#define ICTA_INTSTATUS_PCIC_MSK	        (MSK(1) << ICTA_INTSTATUS_PCIC_SHF)
#define ICTA_INTSTATUS_PCIC_SET	        ICTA_INTSTATUS_PCIC_MSK

/* bit 9: PCIB */
#define ICTA_INTSTATUS_PCIB_SHF	        9
#define ICTA_INTSTATUS_PCIB_MSK	        (MSK(1) << ICTA_INTSTATUS_PCIB_SHF)
#define ICTA_INTSTATUS_PCIB_SET	        ICTA_INTSTATUS_PCIB_MSK

/* bit 8: PCIA */
#define ICTA_INTSTATUS_PCIA_SHF	        8
#define ICTA_INTSTATUS_PCIA_MSK	        (MSK(1) << ICTA_INTSTATUS_PCIA_SHF)
#define ICTA_INTSTATUS_PCIA_SET	        ICTA_INTSTATUS_PCIA_MSK

/* bit 7: NMI */
#define ICTA_INTSTATUS_NMI_SHF	        7
#define ICTA_INTSTATUS_NMI_MSK	        (MSK(1) << ICTA_INTSTATUS_NMI_SHF)
#define ICTA_INTSTATUS_NMI_SET	        ICTA_INTSTATUS_NMI_MSK

/* bit 6: CORELO */
#define ICTA_INTSTATUS_CORELO_SHF	6
#define ICTA_INTSTATUS_CORELO_MSK	(MSK(1) << ICTA_INTSTATUS_CORELO_SHF)
#define ICTA_INTSTATUS_CORELO_SET	ICTA_INTSTATUS_CORELO_MSK

/* bit 5: COREHI */
#define ICTA_INTSTATUS_COREHI_SHF	5
#define ICTA_INTSTATUS_COREHI_MSK	(MSK(1) << ICTA_INTSTATUS_COREHI_SHF)
#define ICTA_INTSTATUS_COREHI_SET	ICTA_INTSTATUS_COREHI_MSK

/* bit 4: RTC */
#define ICTA_INTSTATUS_RTC_SHF	        4
#define ICTA_INTSTATUS_RTC_MSK	        (MSK(1) << ICTA_INTSTATUS_RTC_SHF)
#define ICTA_INTSTATUS_RTC_SET	        ICTA_INTSTATUS_RTC_MSK

/* bit 2: TIM1 */
#define ICTA_INTSTATUS_TIM1_SHF	        2
#define ICTA_INTSTATUS_TIM1_MSK	        (MSK(1) << ICTA_INTSTATUS_TIM1_SHF)
#define ICTA_INTSTATUS_TIM1_SET	        ICTA_INTSTATUS_TIM1_MSK

/* bit 1: TIM0 */
#define ICTA_INTSTATUS_TIM0_SHF	        1
#define ICTA_INTSTATUS_TIM0_MSK	        (MSK(1) << ICTA_INTSTATUS_TIM0_SHF)
#define ICTA_INTSTATUS_TIM0_SET	        ICTA_INTSTATUS_TIM0_MSK

/* bit 0: SER */
#define ICTA_INTSTATUS_SER_SHF	        0
#define ICTA_INTSTATUS_SER_MSK	        (MSK(1) << ICTA_INTSTATUS_SER_SHF)
#define ICTA_INTSTATUS_SER_SET	        ICTA_INTSTATUS_SER_MSK


/**** Number of interrupt lines ****/
#define ICTA_IC_COUNT			20



#endif /* #ifndef ICTA_H */