malta.h

MIPS下的boottloader yamon 的源代码

#define MALTA_STATUS_BIGEND_MSK   (MSK(1) << MALTA_STATUS_BIGEND_SHF)
#define MALTA_STATUS_BIGEND_BIT   MALTA_STATUS_BIGEND_MSK


/******** reg: JMPRS ********/

/* bit 4:2: PCICLK */
#define MALTA_JMPRS_PCICLK_SHF      2
#define MALTA_JMPRS_PCICLK_MSK      (MSK(3) << MALTA_JMPRS_PCICLK_SHF)
#define MALTA_JMPRS_PCICLK_10MHZ    7
#define MALTA_JMPRS_PCICLK_12_5MHZ  4
#define MALTA_JMPRS_PCICLK_16_67MHZ 5
#define MALTA_JMPRS_PCICLK_20MHZ    1
#define MALTA_JMPRS_PCICLK_25MHZ    2
#define MALTA_JMPRS_PCICLK_30MHZ    3
#define MALTA_JMPRS_PCICLK_33_33MHZ 0
#define MALTA_JMPRS_PCICLK_37_5MHZ  6

/* bit 1: EELOCK */
#define MALTA_JMPRS_EELOCK_SHF      1
#define MALTA_JMPRS_EELOCK_MSK      (MSK(1) << MALTA_JMPRS_EELOCK_SHF)
#define MALTA_JMPRS_EELOCK_BIT      MALTA_JMPRS_EELOCK_MSK


/******** reg: SOFTRES ********/

/* bits 7:0: RESET */
#define MALTA_SOFTRES_RESET_SHF     0
#define MALTA_SOFTRES_RESET_MSK     (MSK(8) << MALTA_SOFTRES_RESET_SHF)
#define MALTA_SOFTRES_RESET_GORESET 0x42     /* magic value to reset    */    


/******** reg: BRKRES ********/

/* bits 7:0: WIDTH */
#define MALTA_BRKRES_WIDTH_SHF      0
#define MALTA_BRKRES_WIDTH_MSK      (MSK(8) << MALTA_BRKRES_WIDTH_SHF)


/******** reg: GPOUT ********/

/* bits 7:0: OUTVAL */
#define MALTA_GPOUT_OUTVAL_SHF      0
#define MALTA_GPOUT_OUTVAL_MSK      (MSK(8) << MALTA_GPOUT_OUTVAL_SHF)


/******** reg: GPINP ********/

/* bits 7:0: INPVAL */
#define MALTA_GPINP_INPVAL_SHF      0
#define MALTA_GPINP_INPVAL_MSK      (MSK(8) << MALTA_GPINP_INPVAL_SHF)


/******** reg: I2CINP ********/

#define MALTA_I2CINP_I2CSCL_SHF     1
#define MALTA_I2CINP_I2CSCL_MSK     (MSK(1) << MALTA_I2CINP_I2CSCL_SHF)
#define MALTA_I2CINP_I2CSCL_BIT     MALTA_I2CINP_I2CSCL_MSK

#define MALTA_I2CINP_I2CSDA_SHF     0
#define MALTA_I2CINP_I2CSDA_MSK     (MSK(1) << MALTA_I2CINP_I2CSDA_SHF)
#define MALTA_I2CINP_I2CSDA_BIT     MALTA_I2CINP_I2CSDA_MSK


/******** reg: I2COE ********/

#define MALTA_I2COE_I2CSCL_SHF      1
#define MALTA_I2COE_I2CSCL_MSK      (MSK(1) << MALTA_I2COE_I2CSCL_SHF)
#define MALTA_I2COE_I2CSCL_BIT      MALTA_I2COE_I2CSCL_MSK

#define MALTA_I2COE_I2CSDA_SHF      0
#define MALTA_I2COE_I2CSDA_MSK      (MSK(1) << MALTA_I2COE_I2CSDA_SHF)
#define MALTA_I2COE_I2CSDA_BIT      MALTA_I2COE_I2CSDA_MSK


/******** reg: I2COUT ********/

#define MALTA_I2COUT_I2CSCL_SHF     1
#define MALTA_I2COUT_I2CSCL_MSK     (MSK(1) << MALTA_I2COUT_I2CSCL_SHF)
#define MALTA_I2COUT_I2CSCL_BIT     MALTA_I2COUT_I2CSCL_MSK

#define MALTA_I2COUT_I2CSDA_SHF     0
#define MALTA_I2COUT_I2CSDA_MSK     (MSK(1) << MALTA_I2COUT_I2CSDA_SHF)
#define MALTA_I2COUT_I2CSDA_BIT     MALTA_I2COUT_I2CSDA_MSK


/******** reg: I2CSEL ********/

#define MALTA_I2CSEL_FPGA_SHF       0
#define MALTA_I2CSEL_FPGA_MSK       (MSK(1) << MALTA_I2CSEL_FPGA_SHF)
#define MALTA_I2CSEL_FPGA_BIT       MALTA_I2CSEL_FPGA_MSK



/************************************************************************
 *      PCI definitions
 ************************************************************************/

/*  IO addresses (Physical addresses) for UINT8 access.
 *  Macro PCI_IO_ADDR swaps the 2 lsb bits of the addr in case CPU is
 *  running Big Endian. This is since PIIX4 is a PCI device, and PCI
 *  is always Little Endian.
 */
#define MALTA_PCI0_IO_BASE         MALTA_PCIMEM3_BASE
#define MALTA_PCI0_ADDR( addr )    (MALTA_PCI0_IO_BASE + (addr))
#define MALTA_PCI_IO_ADDR8( addr ) SWAP_BYTEADDR_EL(MALTA_PCI0_ADDR(addr))

/* PIIX4 South Bridge IO access (KSEG1) */
#define MALTA_PIIX4_IO8( addr )    REG8(KSEG1(MALTA_PCI_IO_ADDR8( \
					PIIX4_IO_BRIDGE_START + (addr))))

/* SMSC SuperIO access (KSEG1). Same base as PIIX4 */
#define MALTA_SUPER_IO8( addr )    MALTA_PIIX4_IO8( addr )

/*  PIIX4 RTC (Physical addresses).
 *  Corrected for endianness !
 */
#define MALTA_RTCADR               MALTA_PCI_IO_ADDR8(0x70)
#define MALTA_RTCDAT               MALTA_PCI_IO_ADDR8(0x71)

/*  SuperIO UARTs (Physical addresses). 
 *  Not corrected for endianness (address swapping) since this is done by
 *  driver.
 */
#define MALTA_SMSC_COM1_ADR        0x3f8
#define MALTA_SMSC_COM2_ADR	   0x2f8
#define MALTA_UART0ADR		   MALTA_PCI0_ADDR(MALTA_SMSC_COM1_ADR)
#define MALTA_UART1ADR		   MALTA_PCI0_ADDR(MALTA_SMSC_COM2_ADR)

/*  SuperIO Parallel port (Physical addresses). 
 *  Not corrected for endianness (address swapping) since this is done by
 *  driver.
 */
#define MALTA_SMSC_1284_ADR	   0x378
#define MALTA_1284ADR		   MALTA_PCI0_ADDR(MALTA_SMSC_1284_ADR)

/*  SuperIO Floppy disk (Physical addresses). 
 *  Not corrected for endianness (address swapping) since this is done by
 *  driver.
 */
#define MALTA_SMSC_FDD_ADR	   0x3f0
#define MALTA_FDDADR		   MALTA_PCI0_ADDR(MALTA_SMSC_FDD_ADR)


/*  SuperIO Keyboard, Mouse (Physical addresses). 
 *  Not corrected for endianness (address swapping) since this is done by
 *  driver.
 */
#define MALTA_SMSC_KYBD_ADR	   0x60  /* Fixed 0x60, 0x64 */
#define MALTA_KYBDADR		   MALTA_PCI0_ADDR(MALTA_SMSC_KYBD_ADR)
#define MALTA_SMSC_MOUSE_ADR	   MALTA_SMSC_KYBD_ADR
#define MALTA_MOUSEADR		   MALTA_KYBDADR

/* ADP bit used as IDSEL during configuration cycles */

#define MALTA_IDSEL_SLOT1	   28
#define MALTA_IDSEL_SLOT2	   29
#define MALTA_IDSEL_SLOT3	   30
#define MALTA_IDSEL_SLOT4	   31
#define MALTA_IDSEL_PIIX4	   20
#define MALTA_IDSEL_AM79C973       21
#define MALTA_IDSEL_CRYSTAL	   22

/* PCI device numbers */
#define MALTA_DEVNUM_PIIX4        PCI_IDSEL2DEVNUM(MALTA_IDSEL_PIIX4)
#define MALTA_DEVNUM_AM79C973     PCI_IDSEL2DEVNUM(MALTA_IDSEL_AM79C973)
#define MALTA_DEVNUM_CRYSTAL      PCI_IDSEL2DEVNUM(MALTA_IDSEL_CRYSTAL)
#define MALTA_DEVNUM_PCI_SLOT1    PCI_IDSEL2DEVNUM(MALTA_IDSEL_SLOT1)
#define MALTA_DEVNUM_PCI_SLOT2    PCI_IDSEL2DEVNUM(MALTA_IDSEL_SLOT2)
#define MALTA_DEVNUM_PCI_SLOT3    PCI_IDSEL2DEVNUM(MALTA_IDSEL_SLOT3)
#define MALTA_DEVNUM_PCI_SLOT4    PCI_IDSEL2DEVNUM(MALTA_IDSEL_SLOT4)

/**** IRQ lines for Malta devices ****/

/* PCI INTA..D       */
#define MALTA_INTLINE_PCIA	  10
#define MALTA_INTLINE_PCIB	  10
#define MALTA_INTLINE_PCIC	  11
#define MALTA_INTLINE_PCID	  11
/* PCI slot 1        */
#define MALTA_INTLINE_SLOT1_A	  MALTA_INTLINE_PCIA
#define MALTA_INTLINE_SLOT1_B     MALTA_INTLINE_PCIB
#define MALTA_INTLINE_SLOT1_C     MALTA_INTLINE_PCIC
#define MALTA_INTLINE_SLOT1_D     MALTA_INTLINE_PCID
/* PCI slot 2        */
#define MALTA_INTLINE_SLOT2_A	  MALTA_INTLINE_PCIB
#define MALTA_INTLINE_SLOT2_B	  MALTA_INTLINE_PCIC
#define MALTA_INTLINE_SLOT2_C	  MALTA_INTLINE_PCID
#define MALTA_INTLINE_SLOT2_D	  MALTA_INTLINE_PCIA
/* PCI slot 3        */
#define MALTA_INTLINE_SLOT3_A	  MALTA_INTLINE_PCIC
#define MALTA_INTLINE_SLOT3_B	  MALTA_INTLINE_PCID
#define MALTA_INTLINE_SLOT3_C	  MALTA_INTLINE_PCIA
#define MALTA_INTLINE_SLOT3_D	  MALTA_INTLINE_PCIB
/* PCI slot 4        */
#define MALTA_INTLINE_SLOT4_A	  MALTA_INTLINE_PCID
#define MALTA_INTLINE_SLOT4_B	  MALTA_INTLINE_PCIA
#define MALTA_INTLINE_SLOT4_C	  MALTA_INTLINE_PCIB
#define MALTA_INTLINE_SLOT4_D	  MALTA_INTLINE_PCIC
/* PIIX4/SuperIO devices */
#define MALTA_INTLINE_KYBD	  1
#define MALTA_INTLINE_TTY1	  3
#define MALTA_INTLINE_TTY0	  4
#define MALTA_INTLINE_FDD	  6
#define MALTA_INTLINE_1284	  7
#define MALTA_INTLINE_MOUSE	  12

/* Local PCI devices */
#define MALTA_INTLINE_79C973	  MALTA_INTLINE_PCIB
#define MALTA_INTLINE_4281	  MALTA_INTLINE_PCIC
#define MALTA_INTLINE_PIIX4_USB   MALTA_INTLINE_PCID
#define MALTA_INTLINE_PIIX4_SMB   9

/**** CPU interrupt lines used by devices ****/
#define MALTA_CPUINT_PIIX4	  C0_STATUS_IM_HW0
#define MALTA_CPUINT_64120	  C0_STATUS_IM_HW3

/**** CPU interrupt line used for SMI ****/
#define MALTA_CPUINT_SMI	  C0_STATUS_IM_HW1


/************************************************************************
 *      MISC definitions
 ************************************************************************/

/* Lowest possible frequency for cpu (used during init for conservative
 * setup of timing (e.g. SDRAM refresh)
 */
#define MALTA_CPUFREQ_LOWEST_MHZ  2


#endif /* #ifndef MALTA_H */