pci.h

MIPS下的boottloader yamon 的源代码

/************************************************************************
 *
 *  PCI definitions
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/


#ifndef PCI_H
#define PCI_H


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <syserror.h>

#ifndef _ASSEMBLER_
#include <pci_api.h>
#endif /* #ifndef _ASSEMBLER_ */

/************************************************************************
 *  PCI definitions
*************************************************************************/

#define PCI_MAX_FUNC			8	/* Max functions 	*/
#define PCI_MAX_BUS			256	/* Max busses		*/
#define PCI_MAX_DEV			64	/* Max devices    	*/

/* Alignment requirements of memory/IO ranges set by PCI-PCI bridges	*/
#define PCI_ALIGN_IO		       (1 << 12) /* IO range		*/
#define PCI_ALIGN_MEM		       (1 << 20) /* Memory range	*/


/************************************************************************
 *  Register numbers (derived by offset addresses) and access types
*************************************************************************/

#define PCI_HEADERTYPE0			0
#define PCI_HEADERTYPE1			1
#define PCI_HEADERTYPE_MAX		1

/* Common header (32 bit registers) */
#define PCI_ID				0x00
#define PCI_SC				0x04
#define PCI_CCREV			0x08
#define PCI_BHLC			0x0C
#define PCI_BAR_MIN			0x10
#define PCI_CFG_BASE1		0x14
#define PCI_BAR_MAX			0x24
#define PCI_MMII			0x3C
#define PCI_BAR(number)			(PCI_BAR_MIN + (number)*4)

/* Common header (8 bit registers) */
#define PCI_LATTIM			0x0d
#define PCI_INTLINE			0x3c

/* Header 1 (32 bit registers) */
#define PCI_SSSP			0x18
#define PCI_IO				0x1C
#define PCI_UPPERIO			0x30
#define PCI_MEM				0x20
#define PCI_PREFMEM			0x24
#define PCI_BCII			0x3C
#define PCI_BAR_MAX_PPB		0x14

/* Header 1 (16 bit registers) */
#define PCI_BC				0x3e

/************************************************************************
 *  Register encodings
*************************************************************************/

/* SC */
#define PCI_SC_CMD_IOS_SHF		0
#define PCI_SC_CMD_IOS_MSK		(MSK(1) << PCI_SC_CMD_IOS_SHF)
#define PCI_SC_CMD_IOS_BIT		PCI_SC_CMD_IOS_MSK

#define PCI_SC_CMD_MS_SHF		1
#define PCI_SC_CMD_MS_MSK		(MSK(1) << PCI_SC_CMD_MS_SHF)
#define PCI_SC_CMD_MS_BIT		PCI_SC_CMD_MS_MSK

#define PCI_SC_CMD_BM_SHF		2
#define PCI_SC_CMD_BM_MSK		(MSK(1) << PCI_SC_CMD_BM_SHF)
#define PCI_SC_CMD_BM_BIT		PCI_SC_CMD_BM_MSK

#define PCI_SC_CMD_PERR_SHF		6
#define PCI_SC_CMD_PERR_MSK		(MSK(1) << PCI_SC_CMD_PERR_SHF)
#define PCI_SC_CMD_PERR_BIT		PCI_SC_CMD_PERR_MSK

#define PCI_SC_CMD_SERR_SHF		8
#define PCI_SC_CMD_SERR_MSK		(MSK(1) << PCI_SC_CMD_SERR_SHF)
#define PCI_SC_CMD_SERR_BIT		PCI_SC_CMD_SERR_MSK

#define PCI_SC_CMD_FBB_SHF		9
#define PCI_SC_CMD_FBB_MSK		(MSK(1) << PCI_SC_CMD_FBB_SHF)
#define PCI_SC_CMD_FBB_BIT		PCI_SC_CMD_FBB_MSK

#define PCI_SC_STATUS_FBB_SHF		(16 + 7)
#define PCI_SC_STATUS_FBB_MSK		(MSK(1) << PCI_SC_STATUS_FBB_SHF)
#define PCI_SC_STATUS_FBB_BIT		PCI_SC_STATUS_FBB_MSK

/* BAR */
#define PCI_BAR_IO_SHF			0
#define PCI_BAR_IO_MSK			(MSK(1) << PCI_BAR_IO_SHF)
#define PCI_BAR_IO_BIT			PCI_BAR_IO_MSK

#define PCI_BAR_TYPE_SHF		1
#define PCI_BAR_TYPE_MSK		(MSK(2) << PCI_BAR_TYPE_SHF)
#define PCI_BAR_TYPE_32			0
#define PCI_BAR_TYPE_32_1M		1
#define PCI_BAR_TYPE_64			2
#define PCI_BAR_TYPE_RSVD		3

#define PCI_BAR_PREFETCH_SHF		3
#define PCI_BAR_PREFETCH_MSK		(MSK(1) << PCI_BAR_PREFETCH_SHF)

#define PCI_BAR_IOSIZE_SHF		2
#define PCI_BAR_IOSIZE_MSK		(MSK(30) << PCI_BAR_IOSIZE_SHF)

#define PCI_BAR_MEMSIZE_SHF		4
#define PCI_BAR_MEMSIZE_MSK		(MSK(28) << PCI_BAR_MEMSIZE_SHF)

/* ID */
#define PCI_ID_DEVID_SHF		16
#define PCI_ID_DEVID_MSK		(MSK(16) << PCI_ID_DEVID_SHF)

#define PCI_ID_VENDORID_SHF		0
#define PCI_ID_VENDORID_MSK		(MSK(16) << PCI_ID_VENDORID_SHF)

/* Class Code and Revision ID (CCREV) */
#define PCI_CCREV_CC_SHF	        8	
#define PCI_CCREV_CC_MSK		(MSK(24) << PCI_CCREV_CC_SHF)

#define PCI_CCREV_REVID_SHF		0
#define PCI_CCREV_REVID_MSK		(MSK(8) << PCI_CCREV_REVID_SHF)

/* BIST, Header Type, Lat timer, Cache line size (BHLC) */
#define PCI_BHLC_BIST_SHF	       24
#define PCI_BHLC_BIST_MSK	       (MSK(8) << PCI_BHLC_BIST_SHF)
#define PCI_BHLC_HT_SHF		       16
#define PCI_BHLC_HT_MSK		       (MSK(7) << PCI_BHLC_HT_SHF)
#define PCI_BHLC_MULTI_SHF	       23
#define PCI_BHLC_MULTI_MSK	       (MSK(1) << PCI_BHLC_MULTI_SHF)
#define PCI_BHLC_MULTI_BIT	       PCI_BHLC_MULTI_MSK
#define PCI_BHLC_LT_SHF		       8
#define PCI_BHLC_LT_MSK		       (MSK(8) << PCI_BHLC_LT_SHF)
#define PCI_BHLC_CLS_SHF	       0
#define PCI_BHLC_CLS_MSK	       (MSK(8) << PCI_BHLC_CLS_SHF)

/* Max Lat, Min Gnt, Int pin, Int line (MMII) */
#define PCI_MMII_MAXLAT_SHF	       24
#define PCI_MMII_MAXLAT_MSK	       (MSK(8) << PCI_MMII_MAXLAT_SHF)
#define PCI_MMII_MINGNT_SHF	       16
#define PCI_MMII_MINGNT_MSK	       (MSK(8) << PCI_MMII_MINGNT_SHF)
#define PCI_MMII_INTPIN_SHF	       8
#define PCI_MMII_INTPIN_MSK	       (MSK(8) << PCI_MMII_INTPIN_SHF)

#define PCI_MMII_INTPIN_NU	       0
#define PCI_MMII_INTPIN_A	       1
#define PCI_MMII_INTPIN_B	       2
#define PCI_MMII_INTPIN_C	       3
#define PCI_MMII_INTPIN_D	       4

#define PCI_MMII_INTLINE_SHF           0
#define PCI_MMII_INTLINE_MSK	       (MSK(8) << PCI_MMII_INTLINE_SHF)
#define PCI_MMII_INTLINE_NONE	       0xFF

/* Sec lat, sub bus num, sec bus number, prim bus number (SSSP) */
#define PCI_SSSP_SLT_SHF	       24
#define PCI_SSSP_SLT_MSK	       (MSK(8) << PCI_SSSP_SLT_SHF)
#define PCI_SSSP_SUBBN_SHF	       16
#define PCI_SSSP_SUBBN_MSK	       (MSK(8) << PCI_SSSP_SUBBN_SHF)
#define PCI_SSSP_SECBN_SHF             8
#define PCI_SSSP_SECBN_MSK	       (MSK(8) << PCI_SSSP_SECBN_SHF)
#define PCI_SSSP_PBN_SHF	       0
#define PCI_SSSP_PBN_MSK	       (MSK(8) << PCI_SSSP_PBN_SHF)

/* Bridge control, int pin, int line (BCII) */
#define PCI_BCII_BC_SHF		       16
#define PCI_BCII_BC_MSK		       (MSK(16) << PCI_BCII_BC_SHF)

#define PCI_BCII_BC_PERR_SHF	       (16 + 0)
#define PCI_BCII_BC_PERR_MSK	       (MSK(1) << PCI_BCII_BC_PERR_SHF)
#define PCI_BCII_BC_PERR_BIT	       PCI_BCII_BC_PERR_MSK

#define PCI_BCII_BC_SERR_SHF	       (16 + 1)
#define PCI_BCII_BC_SERR_MSK	       (MSK(1) << PCI_BCII_BC_SERR_SHF)
#define PCI_BCII_BC_SERR_BIT	       PCI_BCII_BC_SERR_MSK

#define PCI_BCII_BC_MA_SHF	       (16 + 5)
#define PCI_BCII_BC_MA_MSK	       (MSK(1) << PCI_BCII_BC_MA_SHF)
#define PCI_BCII_BC_MA_BIT	       PCI_BCII_BC_MA_MSK

#define PCI_BCII_BC_FBB_SHF	       (16 + 7)
#define PCI_BCII_BC_FBB_MSK	       (MSK(1) << PCI_BCII_BC_FBB_SHF)
#define PCI_BCII_BC_FBB_BIT	       PCI_BCII_BC_FBB_MSK

/* IO */
#define PCI_IO_BASE_SHF			0
#define PCI_IO_BASE_MSK			(MSK(8) << PCI_IO_BASE_SHF)
#define PCI_IO_LIMIT_SHF		8
#define PCI_IO_LIMIT_MSK		(MSK(8) << PCI_IO_LIMIT_SHF)

/* UpperIO */
#define PCI_UPPERIO_BASE_SHF		0
#define PCI_UPPERIO_BASE_MSK		(MSK(16) << PCI_UPPERIO_BASE_SHF)
#define PCI_UPPERIO_LIMIT_SHF		16
#define PCI_UPPERIO_LIMIT_MSK		(MSK(16) << PCI_UPPERIO_LIMIT_SHF)

/* Mem */
#define PCI_MEM_BASE_SHF		0
#define PCI_MEM_BASE_MSK		(MSK(16) << PCI_MEM_BASE_SHF)
#define PCI_MEM_LIMIT_SHF		16
#define PCI_MEM_LIMIT_MSK		(MSK(16) << PCI_MEM_LIMIT_SHF)

/* PrefMem */
#define PCI_PREFMEM_BASE_SHF		0
#define PCI_PREFMEM_BASE_MSK		(MSK(16) << PCI_PREFMEM_BASE_SHF)
#define PCI_PREFMEM_LIMIT_SHF		16
#define PCI_PREFMEM_LIMIT_MSK		(MSK(16) << PCI_PREFMEM_LIMIT_SHF)


#ifndef _ASSEMBLER_


/****  Structures and function prototypes used locally in implementation 
 ****  of PCI configuration. 
 ****/


/* Known device */
typedef struct
{
    UINT16  vendorid;
    UINT16  devid;
    UINT8   function;
    UINT8   intline;
    char    *vendor;
    char    *device;
}
t_known_dev;

/* Fixed request for BAR setup */
typedef struct