📄 tcxmaster.lst
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C51 COMPILER V8.02 TCXMASTER 05/04/2008 21:52:43 PAGE 1
C51 COMPILER V8.02, COMPILATION OF MODULE TCXMASTER
OBJECT MODULE PLACED IN tcxmaster.OBJ
COMPILER INVOKED BY: E:\Keil3\C51\BIN\C51.EXE tcxmaster.c OPTIMIZE(6,SPEED) DEBU
-G OBJECTEXTEND CODE SYMBOLS PAGEWIDTH(80)
line level source
1 #pragma NOIV // Do not generate interrupt vecto
-rs
2 //----------------------------------------------------------------
--------------
3 // File: tcxmaster.c
4 // Contents: Hooks required to implement USB peripheral functio
-n.
5 // Code written for FX2 56-pin REVD...
6 // This firmware is used to test the FX ext. master C
-Y3682 DK
7 // Copyright (c) 2001 Cypress Semiconductor All rights reserved
8 //----------------------------------------------------------------
--------------
9 #include "fx2.h"
10 #include "fx2regs.h"
11 #include "fx2sdly.h" // SYNCDELAY macro
12
13 extern BOOL GotSUD; // Received setup data flag
14 extern BOOL Sleep;
15 extern BOOL Rwuen;
16 extern BOOL Selfpwr;
17
18 BYTE Configuration; // Current configuration
19 BYTE AlternateSetting; // Alternate settings
20
21 // EZUSB FX2 PORTA = slave fifo enable(s), when IFCFG[1:0]=11
22 sbit PA0 = IOA ^ 0; // alt. func., INT0#
23 sbit PA1 = IOA ^ 1; // alt. func., INT1#
24 // sbit PA2 = IOA ^ 2; // is SLOE
25 sbit PA3 = IOA ^ 3; // alt. func., WU2
26 // sbit PA4 = IOA ^ 4; // is FIFOADR0
27 // sbit PA5 = IOA ^ 5; // is FIFOADR1
28 // sbit PA6 = IOA ^ 6; // is PKTEND
29 // sbit PA7 = IOA ^ 7; // is FLAGD
30
31 // EZUSB FX2 PORTC i/o... port NA for 56-pin FX2
32 // sbit PC0 = IOC ^ 0;
33 // sbit PC1 = IOC ^ 1;
34 // sbit PC2 = IOC ^ 2;
35 // sbit PC3 = IOC ^ 3;
36 // sbit PC4 = IOC ^ 4;
37 // sbit PC5 = IOC ^ 5;
38 // sbit PC6 = IOC ^ 6;
39 // sbit PC7 = IOC ^ 7;
40
41 // EZUSB FX2 PORTB = FD[7:0], when IFCFG[1:0]=11
42 // sbit PB0 = IOB ^ 0;
43 // sbit PB1 = IOB ^ 1;
44 // sbit PB2 = IOB ^ 2;
45 // sbit PB3 = IOB ^ 3;
46 // sbit PB4 = IOB ^ 4;
47 // sbit PB5 = IOB ^ 5;
48 // sbit PB6 = IOB ^ 6;
49 // sbit PB7 = IOB ^ 7;
C51 COMPILER V8.02 TCXMASTER 05/04/2008 21:52:43 PAGE 2
50
51 // EZUSB FX2 PORTD = FD[15:8], when IFCFG[1:0]=11 and WORDWIDE=1
52 sbit PD0 = IOD ^ 0;
53 sbit PD1 = IOD ^ 1;
54 sbit PD2 = IOD ^ 2;
55 sbit PD3 = IOD ^ 3;
56 sbit PD4 = IOD ^ 4;
57 sbit PD5 = IOD ^ 5;
58 sbit PD6 = IOD ^ 6;
59 sbit PD7 = IOD ^ 7;
60
61 // EZUSB FX2 PORTE is not bit-addressable...
62
63 //----------------------------------------------------------------
--------------
64 // Task Dispatcher hooks
65 // The following hooks are called by the task dispatcher.
66 //----------------------------------------------------------------
--------------
67 void TD_Init( void )
68 { // Called once at startup
69 1
70 1 CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz opera
-tion
71 1
72 1 IFCONFIG = 0xCB; //异步操作
73 1 // IFCLKSRC=1 , FIFOs executes on internal clk source
74 1 // xMHz=1 , 48MHz internal clk rate
75 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
76 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal cl
-k
77 1 // ASYNC=1 , master samples asynchronous
78 1 // GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], deb
-ug WF
79 1 // IFCFG[1:0]=11, FX2 in slave FIFO mode
80 1
81 1
82 1 // Registers which require a synchronization delay, see section
-15.14
83 1 // FIFORESET FIFOPINPOLAR
84 1 // INPKTEND OUTPKTEND
85 1 // EPxBCH:L REVCTL
86 1 // GPIFTCB3 GPIFTCB2
87 1 // GPIFTCB1 GPIFTCB0
88 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
89 1 // EPxFIFOCFG EPxGPIFFLGSEL
90 1 // PINFLAGSxx EPxFIFOIRQ
91 1 // EPxFIFOIE GPIFIRQ
92 1 // GPIFIE GPIFADRH:L
93 1 // UDMACRCH:L EPxGPIFTRIG
94 1 // GPIFTRIG
95 1
96 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as wel
-l...
97 1 // ...these have been replaced by GPIFTC[B3:B0] registers
98 1
99 1 EP2CFG=0Xf8; //IN INT 4*1024
100 1 SYNCDELAY;
101 1 EP4CFG=0X20; //无效
102 1 SYNCDELAY;
103 1 EP6CFG=0X20; //无效
104 1 SYNCDELAY;
C51 COMPILER V8.02 TCXMASTER 05/04/2008 21:52:43 PAGE 3
105 1 EP8CFG=0X60; //无效
106 1
107 1
108 1
109 1 SYNCDELAY;
110 1 FIFORESET = 0x80; // activate NAK-ALL to avoid race
-conditions
111 1 SYNCDELAY; // see TRM section 15.14
112 1 FIFORESET = 0x02; // reset, FIFO 2
113 1 SYNCDELAY; //
114 1 FIFORESET = 0x04; // reset, FIFO 4
115 1 SYNCDELAY; //
116 1 FIFORESET = 0x06; // reset, FIFO 6
117 1 SYNCDELAY; //
118 1 FIFORESET = 0x08; // reset, FIFO 8
119 1 SYNCDELAY; //
120 1 FIFORESET = 0x00; // deactivate NAK-ALL
121 1
122 1
123 1
124 1 SYNCDELAY;
125 1 PINFLAGSAB = 0xc8; // FLAGA - fixed EP2EF, FLAGB - fi
-xed EP2FF
126 1 SYNCDELAY;
127 1 //PINFLAGSCD = 0xFE; // FLAGC - fixed EP6FF, FLAGD -
-fixed EP8FF
128 1 //SYNCDELAY;
129 1 PORTACFG |= 0x80; // FLAGD, set alt. func. of PA7 pi
-n
130 1 SYNCDELAY;
131 1 FIFOPINPOLAR = 0x00; // pktend,sloe,slrd,slwr,ef,ff低电
-平有效
132 1 SYNCDELAY;
133 1
134 1 // handle the case where we were already in AUTO mode...
135 1 EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0
136 1 SYNCDELAY;
137 1
138 1 EP2FIFOCFG = 0x0C; // AUTOIN=1, ZEROLENIN=1, WORDWIDE
-=0
139 1 SYNCDELAY;
140 1
141 1
142 1 EP2AUTOINLENH = 0x04 ; //端点2自动提交1K
143 1 SYNCDELAY;
144 1 SYNCDELAY;
145 1 EP2AUTOINLENL = 0x00;
146 1 SYNCDELAY;
147 1
148 1 }
149
150
151
152
153
154 void TD_Poll( void )
155 { // Called repeatedly while the device is idle
156 1 /*
157 1 WORD i;
158 1
159 1 //**** IN 端点进行数据提交 ******
160 1 if(!(EP2468STAT & bmEP2FULL)) //若不满 , bmEP8FULL
C51 COMPILER V8.02 TCXMASTER 05/04/2008 21:52:43 PAGE 4
161 1 {
162 1 for( i = 0x0000; i < 0x400; i++ )
163 1 {
164 1 EP2FIFOBUF[i]=(BYTE)(i&0xff);
165 1 }
166 1 EP2BCH = 0x04;
167 1 SYNCDELAY;
168 1 EP2BCL = 0x00; //IN型的端点就不需要重载了
169 1
170 1 }
171 1
172 1 */
173 1
174 1 // ...nothing to do... slave fifo's are in AUTO mode...
175 1
176 1 }
177
178 BOOL TD_Suspend( void )
179 { // Called before the device goes into suspend mode
180 1 return( TRUE );
181 1 }
182
183 BOOL TD_Resume( void )
184 { // Called after the device resumes
185 1 return( TRUE );
186 1 }
187
188 //----------------------------------------------------------------
--------------
189 // Device Request hooks
190 // The following hooks are called by the end point 0 device requ
-est parser.
191 //----------------------------------------------------------------
--------------
192 BOOL DR_GetDescriptor( void )
193 {
194 1 return( TRUE );
195 1 }
196
197 BOOL DR_SetConfiguration( void )
198 { // Called when a Set Configuration command is received
199 1
200 1 if( EZUSB_HIGHSPEED( ) )
201 1 { // ...FX2 in high speed mode
202 2 EP6AUTOINLENH = 0x02;
203 2 SYNCDELAY;
204 2 SYNCDELAY;
205 2 EP6AUTOINLENL = 0x00;
206 2 SYNCDELAY;
207 2 }
208 1 else
209 1 { // ...FX2 in full speed mode
210 2 EP6AUTOINLENH = 0x00;
211 2 SYNCDELAY;
212 2 // EP8AUTOINLENH = 0x00; // set core AUTO commit len = 64 byt
-es
213 2 SYNCDELAY;
214 2 EP6AUTOINLENL = 0x40;
215 2 SYNCDELAY;
216 2 // EP8AUTOINLENL = 0x40;
217 2 }
218 1
C51 COMPILER V8.02 TCXMASTER 05/04/2008 21:52:43 PAGE 5
219 1 Configuration = SETUPDAT[ 2 ];
220 1 return( TRUE ); // Handled by user code
221 1 }
222
223 BOOL DR_GetConfiguration( void )
224 { // Called when a Get Configuration command is received
225 1 EP0BUF[ 0 ] = Configuration;
226 1 EP0BCH = 0;
227 1 EP0BCL = 1;
228 1 return(TRUE); // Handled by user code
229 1 }
230
231 BOOL DR_SetInterface( void )
232 { // Called when a Set Interface command is received
233 1 AlternateSetting = SETUPDAT[ 2 ];
234 1 return( TRUE ); // Handled by user code
235 1 }
236
237 BOOL DR_GetInterface( void )
238 { // Called when a Set Interface command is received
239 1 EP0BUF[ 0 ] = AlternateSetting;
240 1 EP0BCH = 0;
241 1 EP0BCL = 1;
242 1 return( TRUE ); // Handled by user code
243 1 }
244
245 BOOL DR_GetStatus( void )
246 {
247 1 return( TRUE );
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