📄 pic16f946.h
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static bank1 bit RBPU @ ((unsigned)&OPTION*8)+7;
// Alternate definition for backward compatibility
static bank1 bit RABPU @ ((unsigned)&OPTION*8)+7;
/* Definitions for TRISA register */
static bank1 bit TRISA0 @ ((unsigned)&TRISA*8)+0;
static bank1 bit TRISA1 @ ((unsigned)&TRISA*8)+1;
static bank1 bit TRISA2 @ ((unsigned)&TRISA*8)+2;
static bank1 bit TRISA3 @ ((unsigned)&TRISA*8)+3;
static bank1 bit TRISA4 @ ((unsigned)&TRISA*8)+4;
static bank1 bit TRISA5 @ ((unsigned)&TRISA*8)+5;
static bank1 bit TRISA6 @ ((unsigned)&TRISA*8)+6;
static bank1 bit TRISA7 @ ((unsigned)&TRISA*8)+7;
/* Definitions for TRISB register */
static volatile bank1 bit TRISB0 @ ((unsigned)&TRISB*8)+0;
static volatile bank1 bit TRISB1 @ ((unsigned)&TRISB*8)+1;
static volatile bank1 bit TRISB2 @ ((unsigned)&TRISB*8)+2;
static volatile bank1 bit TRISB3 @ ((unsigned)&TRISB*8)+3;
static volatile bank1 bit TRISB4 @ ((unsigned)&TRISB*8)+4;
static volatile bank1 bit TRISB5 @ ((unsigned)&TRISB*8)+5;
static volatile bank1 bit TRISB6 @ ((unsigned)&TRISB*8)+6;
static volatile bank1 bit TRISB7 @ ((unsigned)&TRISB*8)+7;
/* Definitions for TRISC register */
static volatile bank1 bit TRISC0 @ ((unsigned)&TRISC*8)+0;
static volatile bank1 bit TRISC1 @ ((unsigned)&TRISC*8)+1;
static volatile bank1 bit TRISC2 @ ((unsigned)&TRISC*8)+2;
static volatile bank1 bit TRISC3 @ ((unsigned)&TRISC*8)+3;
static volatile bank1 bit TRISC4 @ ((unsigned)&TRISC*8)+4;
static volatile bank1 bit TRISC5 @ ((unsigned)&TRISC*8)+5;
static volatile bank1 bit TRISC6 @ ((unsigned)&TRISC*8)+6;
static volatile bank1 bit TRISC7 @ ((unsigned)&TRISC*8)+7;
/* Definitions for TRISD register */
static volatile bank1 bit TRISD0 @ ((unsigned)&TRISD*8)+0;
static volatile bank1 bit TRISD1 @ ((unsigned)&TRISD*8)+1;
static volatile bank1 bit TRISD2 @ ((unsigned)&TRISD*8)+2;
static volatile bank1 bit TRISD3 @ ((unsigned)&TRISD*8)+3;
static volatile bank1 bit TRISD4 @ ((unsigned)&TRISD*8)+4;
static volatile bank1 bit TRISD5 @ ((unsigned)&TRISD*8)+5;
static volatile bank1 bit TRISD6 @ ((unsigned)&TRISD*8)+6;
static volatile bank1 bit TRISD7 @ ((unsigned)&TRISD*8)+7;
/* Definitions for TRISE register */
static volatile bank1 bit TRISE0 @ ((unsigned)&TRISE*8)+0;
static volatile bank1 bit TRISE1 @ ((unsigned)&TRISE*8)+1;
static volatile bank1 bit TRISE2 @ ((unsigned)&TRISE*8)+2;
static volatile bank1 bit TRISE3 @ ((unsigned)&TRISE*8)+3;
static volatile bank1 bit TRISE4 @ ((unsigned)&TRISE*8)+4;
static volatile bank1 bit TRISE5 @ ((unsigned)&TRISE*8)+5;
static volatile bank1 bit TRISE6 @ ((unsigned)&TRISE*8)+6;
static volatile bank1 bit TRISE7 @ ((unsigned)&TRISE*8)+7;
/* Definitions for PIE1 register */
static bank1 bit TMR1IE @ ((unsigned)&PIE1*8)+0;
static bank1 bit TMR2IE @ ((unsigned)&PIE1*8)+1;
static bank1 bit CCP1IE @ ((unsigned)&PIE1*8)+2;
static bank1 bit SSPIE @ ((unsigned)&PIE1*8)+3;
static bank1 bit TXIE @ ((unsigned)&PIE1*8)+4;
static bank1 bit RCIE @ ((unsigned)&PIE1*8)+5;
static bank1 bit ADIE @ ((unsigned)&PIE1*8)+6;
static bank1 bit EEIE @ ((unsigned)&PIE1*8)+7;
/* Definitions for PIE2 register */
static bank1 bit CCP2IE @ ((unsigned)&PIE2*8)+0;
static bank1 bit LVDIE @ ((unsigned)&PIE2*8)+2;
static bank1 bit LCDIE @ ((unsigned)&PIE2*8)+4;
static bank1 bit C1IE @ ((unsigned)&PIE2*8)+5;
static bank1 bit C2IE @ ((unsigned)&PIE2*8)+6;
static bank1 bit OSFIE @ ((unsigned)&PIE2*8)+7;
/* Definitions for PCON register */
static volatile bank1 bit BOR @ ((unsigned)&PCON*8)+0;
static volatile bank1 bit POR @ ((unsigned)&PCON*8)+1;
static bank1 bit SBOREN @ ((unsigned)&PCON*8)+4;
/* Definitions for OSCCON register */
static bank1 bit SCS @ ((unsigned)&OSCCON*8)+0;
static volatile bank1 bit LTS @ ((unsigned)&OSCCON*8)+1;
static volatile bank1 bit HTS @ ((unsigned)&OSCCON*8)+2;
static volatile bank1 bit OSTS @ ((unsigned)&OSCCON*8)+3;
static bank1 bit IRCF0 @ ((unsigned)&OSCCON*8)+4;
static bank1 bit IRCF1 @ ((unsigned)&OSCCON*8)+5;
static bank1 bit IRCF2 @ ((unsigned)&OSCCON*8)+6;
/* Definitions for OSCTUNE register */
static bank1 bit TUN0 @ ((unsigned)&OSCTUNE*8)+0;
static bank1 bit TUN1 @ ((unsigned)&OSCTUNE*8)+1;
static bank1 bit TUN2 @ ((unsigned)&OSCTUNE*8)+2;
static bank1 bit TUN3 @ ((unsigned)&OSCTUNE*8)+3;
static bank1 bit TUN4 @ ((unsigned)&OSCTUNE*8)+4;
/* Definitions for ANSEL register */
static bank1 bit ANS0 @ ((unsigned)&ANSEL*8)+0;
static bank1 bit ANS1 @ ((unsigned)&ANSEL*8)+1;
static bank1 bit ANS2 @ ((unsigned)&ANSEL*8)+2;
static bank1 bit ANS3 @ ((unsigned)&ANSEL*8)+3;
static bank1 bit ANS4 @ ((unsigned)&ANSEL*8)+4;
static bank1 bit ANS5 @ ((unsigned)&ANSEL*8)+5;
static bank1 bit ANS6 @ ((unsigned)&ANSEL*8)+6;
static bank1 bit ANS7 @ ((unsigned)&ANSEL*8)+7;
/* Definitions for SSPSTAT register */
static volatile bank1 bit BF @ ((unsigned)&SSPSTAT*8)+0;
static volatile bank1 bit UA @ ((unsigned)&SSPSTAT*8)+1;
static volatile bank1 bit RW @ ((unsigned)&SSPSTAT*8)+2;
static volatile bank1 bit START @ ((unsigned)&SSPSTAT*8)+3;
static volatile bank1 bit STOP @ ((unsigned)&SSPSTAT*8)+4;
static volatile bank1 bit DA @ ((unsigned)&SSPSTAT*8)+5;
static bank1 bit CKE @ ((unsigned)&SSPSTAT*8)+6;
static bank1 bit SMP @ ((unsigned)&SSPSTAT*8)+7;
/* Definitions for WPUB register */
static bank1 bit WPUB0 @ ((unsigned)&WPUB*8)+0;
static bank1 bit WPUB1 @ ((unsigned)&WPUB*8)+1;
static bank1 bit WPUB2 @ ((unsigned)&WPUB*8)+2;
static bank1 bit WPUB3 @ ((unsigned)&WPUB*8)+3;
static bank1 bit WPUB4 @ ((unsigned)&WPUB*8)+4;
static bank1 bit WPUB5 @ ((unsigned)&WPUB*8)+5;
static bank1 bit WPUB6 @ ((unsigned)&WPUB*8)+6;
static bank1 bit WPUB7 @ ((unsigned)&WPUB*8)+7;
/* Definitions for IOCB register */
static bank1 bit IOCB4 @ ((unsigned)&IOCB*8)+4;
static bank1 bit IOCB5 @ ((unsigned)&IOCB*8)+5;
static bank1 bit IOCB6 @ ((unsigned)&IOCB*8)+6;
static bank1 bit IOCB7 @ ((unsigned)&IOCB*8)+7;
/* Definitions for CMCON1 register */
static bank1 bit C2SYNC @ ((unsigned)&CMCON1*8)+0;
static bank1 bit T1GSS @ ((unsigned)&CMCON1*8)+1;
/* Definitions for TXSTA register */
static volatile bank1 bit TX9D @ ((unsigned)&TXSTA*8)+0;
static volatile bank1 bit TRMT @ ((unsigned)&TXSTA*8)+1;
static bank1 bit BRGH @ ((unsigned)&TXSTA*8)+2;
static bank1 bit SYNC @ ((unsigned)&TXSTA*8)+4;
static bank1 bit TXEN @ ((unsigned)&TXSTA*8)+5;
static bank1 bit TX9 @ ((unsigned)&TXSTA*8)+6;
static bank1 bit CSRC @ ((unsigned)&TXSTA*8)+7;
/* Definitions for SPBRG register */
static bank1 bit SPBRG0 @ ((unsigned)&SPBRG*8)+0;
static bank1 bit SPBRG1 @ ((unsigned)&SPBRG*8)+1;
static bank1 bit SPBRG2 @ ((unsigned)&SPBRG*8)+2;
static bank1 bit SPBRG3 @ ((unsigned)&SPBRG*8)+3;
static bank1 bit SPBRG4 @ ((unsigned)&SPBRG*8)+4;
static bank1 bit SPBRG5 @ ((unsigned)&SPBRG*8)+5;
static bank1 bit SPBRG6 @ ((unsigned)&SPBRG*8)+6;
static bank1 bit SPBRG7 @ ((unsigned)&SPBRG*8)+7;
/* Definitions for CMCON0 register */
static bank1 bit CM0 @ ((unsigned)&CMCON0*8)+0;
static bank1 bit CM1 @ ((unsigned)&CMCON0*8)+1;
static bank1 bit CM2 @ ((unsigned)&CMCON0*8)+2;
static bank1 bit CIS @ ((unsigned)&CMCON0*8)+3;
static bank1 bit C1INV @ ((unsigned)&CMCON0*8)+4;
static bank1 bit C2INV @ ((unsigned)&CMCON0*8)+5;
static volatile bank1 bit C1OUT @ ((unsigned)&CMCON0*8)+6;
static volatile bank1 bit C2OUT @ ((unsigned)&CMCON0*8)+7;
/* Definitions for VRCON register */
static bank1 bit VR0 @ ((unsigned)&VRCON*8)+0;
static bank1 bit VR1 @ ((unsigned)&VRCON*8)+1;
static bank1 bit VR2 @ ((unsigned)&VRCON*8)+2;
static bank1 bit VR3 @ ((unsigned)&VRCON*8)+3;
static bank1 bit VRR @ ((unsigned)&VRCON*8)+5;
static bank1 bit VREN @ ((unsigned)&VRCON*8)+7;
/* Definitions for ADCON1 register */
static bank1 bit ADCS0 @ ((unsigned)&ADCON1*8)+4;
static bank1 bit ADCS1 @ ((unsigned)&ADCON1*8)+5;
static bank1 bit ADCS2 @ ((unsigned)&ADCON1*8)+6;
/* Definitions for WDTCON register */
static bank2 bit SWDTEN @ ((unsigned)&WDTCON*8)+0;
static bank2 bit WDTPS0 @ ((unsigned)&WDTCON*8)+1;
static bank2 bit WDTPS1 @ ((unsigned)&WDTCON*8)+2;
static bank2 bit WDTPS2 @ ((unsigned)&WDTCON*8)+3;
static bank2 bit WDTPS3 @ ((unsigned)&WDTCON*8)+4;
/* Definitions for LCDCON register */
static bank2 bit LMUX0 @ ((unsigned)&LCDCON*8)+0;
static bank2 bit LMUX1 @ ((unsigned)&LCDCON*8)+1;
static bank2 bit CS0 @ ((unsigned)&LCDCON*8)+2;
static bank2 bit CS1 @ ((unsigned)&LCDCON*8)+3;
static bank2 bit VLCDEN @ ((unsigned)&LCDCON*8)+4;
static volatile bank2 bit WERR @ ((unsigned)&LCDCON*8)+5;
static bank2 bit SLPEN @ ((unsigned)&LCDCON*8)+6;
static bank2 bit LCDEN @ ((unsigned)&LCDCON*8)+7;
/* Definitions for LCDPS register */
static bank2 bit LP0 @ ((unsigned)&LCDPS*8)+0;
static bank2 bit LP1 @ ((unsigned)&LCDPS*8)+1;
static bank2 bit LP2 @ ((unsigned)&LCDPS*8)+2;
static bank2 bit LP3 @ ((unsigned)&LCDPS*8)+3;
static volatile bank2 bit WA @ ((unsigned)&LCDPS*8)+4;
static volatile bank2 bit LCDA @ ((unsigned)&LCDPS*8)+5;
static bank2 bit BIASMD @ ((unsigned)&LCDPS*8)+6;
static bank2 bit WFT @ ((unsigned)&LCDPS*8)+7;
/* Definitions for LVDCON register */
static bank2 bit LVDL0 @ ((unsigned)&LVDCON*8)+0;
static bank2 bit LVDL1 @ ((unsigned)&LVDCON*8)+1;
static bank2 bit LVDL2 @ ((unsigned)&LVDCON*8)+2;
static bank2 bit LVDEN @ ((unsigned)&LVDCON*8)+4;
static volatile bank2 bit IRVST @ ((unsigned)&LVDCON*8)+5;
/* Definitions for LCDDATA0 register */
static bank2 bit SEG0COM0 @ ((unsigned)&LCDDATA0*8)+0;
static bank2 bit SEG1COM0 @ ((unsigned)&LCDDATA0*8)+1;
static bank2 bit SEG2COM0 @ ((unsigned)&LCDDATA0*8)+2;
static bank2 bit SEG3COM0 @ ((unsigned)&LCDDATA0*8)+3;
static bank2 bit SEG4COM0 @ ((unsigned)&LCDDATA0*8)+4;
static bank2 bit SEG5COM0 @ ((unsigned)&LCDDATA0*8)+5;
static bank2 bit SEG6COM0 @ ((unsigned)&LCDDATA0*8)+6;
static bank2 bit SEG7COM0 @ ((unsigned)&LCDDATA0*8)+7;
/* Definitions for LCDDATA1 register */
static bank2 bit SEG8COM0 @ ((unsigned)&LCDDATA1*8)+0;
static bank2 bit SEG9COM0 @ ((unsigned)&LCDDATA1*8)+1;
static bank2 bit SEG10COM0 @ ((unsigned)&LCDDATA1*8)+2;
static bank2 bit SEG11COM0 @ ((unsigned)&LCDDATA1*8)+3;
static bank2 bit SEG12COM0 @ ((unsigned)&LCDDATA1*8)+4;
static bank2 bit SEG13COM0 @ ((unsigned)&LCDDATA1*8)+5;
static bank2 bit SEG14COM0 @ ((unsigned)&LCDDATA1*8)+6;
static bank2 bit SEG15COM0 @ ((unsigned)&LCDDATA1*8)+7;
/* Definitions for LCDDATA2 register */
static bank2 bit SEG16COM0 @ ((unsigned)&LCDDATA2*8)+0;
static bank2 bit SEG17COM0 @ ((unsigned)&LCDDATA2*8)+1;
static bank2 bit SEG18COM0 @ ((unsigned)&LCDDATA2*8)+2;
static bank2 bit SEG19COM0 @ ((unsigned)&LCDDATA2*8)+3;
static bank2 bit SEG20COM0 @ ((unsigned)&LCDDATA2*8)+4;
static bank2 bit SEG21COM0 @ ((unsigned)&LCDDATA2*8)+5;
static bank2 bit SEG22COM0 @ ((unsigned)&LCDDATA2*8)+6;
static bank2 bit SEG23COM0 @ ((unsigned)&LCDDATA2*8)+7;
/* Definitions for LCDDATA3 register */
static bank2 bit SEG0COM1 @ ((unsigned)&LCDDATA3*8)+0;
static bank2 bit SEG1COM1 @ ((unsigned)&LCDDATA3*8)+1;
static bank2 bit SEG2COM1 @ ((unsigned)&LCDDATA3*8)+2;
static bank2 bit SEG3COM1 @ ((unsigned)&LCDDATA3*8)+3;
static bank2 bit SEG4COM1 @ ((unsigned)&LCDDATA3*8)+4;
static bank2 bit SEG5COM1 @ ((unsigned)&LCDDATA3*8)+5;
static bank2 bit SEG6COM1 @ ((unsigned)&LCDDATA3*8)+6;
static bank2 bit SEG7COM1 @ ((unsigned)&LCDDATA3*8)+7;
/* Definitions for LCDDATA4 register */
static bank2 bit SEG8COM1 @ ((unsigned)&LCDDATA4*8)+0;
static bank2 bit SEG9COM1 @ ((unsigned)&LCDDATA4*8)+1;
static bank2 bit SEG10COM1 @ ((unsigned)&LCDDATA4*8)+2;
static bank2 bit SEG11COM1 @ ((unsigned)&LCDDATA4*8)+3;
static bank2 bit SEG12COM1 @ ((unsigned)&LCDDATA4*8)+4;
static bank2 bit SEG13COM1 @ ((unsigned)&LCDDATA4*8)+5;
static bank2 bit SEG14COM1 @ ((unsigned)&LCDDATA4*8)+6;
static bank2 bit SEG15COM1 @ ((unsigned)&LCDDATA4*8)+7;
/* Definitions for LCDDATA5 register */
static bank2 bit SEG16COM1 @ ((unsigned)&LCDDATA5*8)+0;
static bank2 bit SEG17COM1 @ ((unsigned)&LCDDATA5*8)+1;
static bank2 bit SEG18COM1 @ ((unsigned)&LCDDATA5*8)+2;
static bank2 bit SEG19COM1 @ ((unsigned)&LCDDATA5*8)+3;
static bank2 bit SEG20COM1 @ ((unsigned)&LCDDATA5*8)+4;
static bank2 bit SEG21COM1 @ ((unsigned)&LCDDATA5*8)+5;
static bank2 bit SEG22COM1 @ ((unsigned)&LCDDATA5*8)+6;
static bank2 bit SEG23COM1 @ ((unsigned)&LCDDATA5*8)+7;
/* Definitions for LCDDATA6 register */
static bank2 bit SEG0COM2 @ ((unsigned)&LCDDATA6*8)+0;
static bank2 bit SEG1COM2 @ ((unsigned)&LCDDATA6*8)+1;
static bank2 bit SEG2COM2 @ ((unsigned)&LCDDATA6*8)+2;
static bank2 bit SEG3COM2 @ ((unsigned)&LCDDATA6*8)+3;
static bank2 bit SEG4COM2 @ ((unsigned)&LCDDATA6*8)+4;
static bank2 bit SEG5COM2 @ ((unsigned)&LCDDATA6*8)+5;
static bank2 bit SEG6COM2 @ ((unsigned)&LCDDATA6*8)+6;
static bank2 bit SEG7COM2 @ ((unsigned)&LCDDATA6*8)+7;
/* Definitions for LCDDATA7 register */
static bank2 bit SEG8COM2 @ ((unsigned)&LCDDATA7*8)+0;
static bank2 bit SEG9COM2 @ ((unsigned)&LCDDATA7*8)+1;
static bank2 bit SEG10COM2 @ ((unsigned)&LCDDATA7*8)+2;
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