start.s

移植好的杨创utu2440F ARM9 的uboot1.1.4代码

/*
 *  armboot - Startup Code for ARM920 CPU-core
 *
 *  Copyright (c) 2001	Marius Gr鰃er <[e-mail]>
 *  Copyright (c) 2002	Alex Z黳ke <[e-mail]>
 *  Copyright (c) 2002	Gary Jennejohn <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <config.h>
#include <version.h>


/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:	b       reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

_TEXT_BASE:
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
	.word __bss_start

.globl _bss_end
_bss_end:
	.word _end

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif


/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode

	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0
*/	 

/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
# define pWTCON		0x15300000
# define INTMSK		0x14400008	/* Interupt-Controller base addresses */
# define CLKDIVN	0x14800014	/* clock divisor register */
#elif defined(CONFIG_S3C2410)||defined(CONFIG_S3C2440)
# define pWTCON		0x53000000
# define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
# define INTSUBMSK	0x4A00001C
# define CLKDIVN	0x4C000014	/* clock divisor register */
#endif

#define CLK_CTL_BASE	0x4C000000
#define oLOCKTIME		0x00	/* R/W, PLL lock time count register */
#define oMPLLCON		0x04	/* R/W, MPLL configuration register */
#define oUPLLCON		0x08	/* R/W, UPLL configuration register */
#define oCLKCON			0x0C	/* R/W, Clock generator control reg. */
#define oCLKSLOW		0x10	/* R/W, Slow clock control register */
#define oCLKDIVN		0x14	/* R/W, Clock divider control */
#define CLKDVIN_406_148         0x05	/*1:4:8 */
#define vUPLLCON_NOW_USER       0x38022/*((MDIV_48 << 12) | (PDIV_48 << 4) | (SDIV_48))  48Mhz for upll*/

#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)||defined(CONFIG_S3C2440)
	ldr     r0, =pWTCON
	mov     r1, #0x0
	str     r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov	r1, #0xffffffff
	ldr	r0, =INTMSK
	str	r1, [r0]
# if defined(CONFIG_S3C2410)
	ldr	r1, =0x3ff
	ldr	r0, =INTSUBMSK
	str	r1, [r0]
# endif
#if defined(CONFIG_S3C2440)
	ldr	r1, =0x7fff	/*intsubmsk*/
	ldr	r0, =INTSUBMSK
	str	r1, [r0]
#endif

#if defined(CONFIG_S3C2440)
	@ initialise system clocks

	mov	r1, #CLK_CTL_BASE
	mvn	r2, #0xff000000
	str	r2, [r1, #oLOCKTIME]
	
	mov	r1, #CLK_CTL_BASE
	@ldr	r2, #CLKDVIN_406_148
	ldr     r2, =0x05
	str	r2, [r1, #oCLKDIVN]		/*1:4:8,*/

	mrc	p15, 0, r1, c1, c0, 0		@ read ctrl register 
	orr	r1, r1, #0xc0000000		@ Asynchronous  
	mcr	p15, 0, r1, c1, c0, 0		@ write ctrl register

	ldr	r0, =0x4C000008
@@    ldr r1, #vUPLLCON_NOW_USER	/*upll 48Mhz*/
	ldr r1,=0x38022
        str     r1, [r0]
 
/* see Spec , approximately 7 nop are needed.*/
    nop
    nop
    nop
    nop
    nop     @ wait until upll has the effect
    nop
    nop
    nop
/* end UPLL setup */

/* Mpll(CPU clock) setup: 406Mhz.
=0x7f021,
#define MDIV_406_148        0x7f
#define PDIV_406_148        0x02
#define SDIV_406_148        0x01
*/
	mov	r1, #CLK_CTL_BASE
	ldr 	r2, =0x7f021	@mpll_value_USER@ clock user set
	str	r2, [r1, #oMPLLCON]
	bl	memsetup
#else
	/* FCLK:HCLK:PCLK = 1:2:4 */
	/* default FCLK is 120 MHz ! */
	ldr	r0, =CLKDIVN
	mov	r1, #3
	str	r1, [r0]
#endif /*CONFIG_2440*/
#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 ||defined(CONFIG_S3C2440)*/




	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

#if  defined(CONFIG_S3C2440)
	@ All LED on
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_F
	ldr	r2,=0x55aa			/* Bit 7~4:output Led, bit 3~0: INT for keypad	*/
	str	r2, [r1, #oGPIO_CON]
	mov	r2, #0xff			/*pull up func is disabled, then pin is forcde to lowelevel*/
	str	r2, [r1, #oGPIO_UP]
	mov	r2, #0x10			/*light 3*/
	str	r2, [r1, #oGPIO_DAT]

/*jun uart*/	
  @ set GPIO for UART
        mov     r1, #GPIO_CTL_BASE
        add     r1, r1, #oGPIO_H
        ldr     r2, gpio_con_uart
        str     r2, [r1, #oGPIO_CON]
        ldr     r2, gpio_up_uart
        str     r2, [r1, #oGPIO_UP]
        bl      InitUART
#endif


#if  defined(CONFIG_S3C2440)
        @ Print current Program Counter
        ldr     r1, SerBase
        mov     r0, #'\r'
        bl      PrintChar
        mov     r0, #'\n'
        bl      PrintChar
        mov     r0, #'@'
        bl      PrintChar
	mov     r0, #'1'
	bl 	PrintChar
	ldr	r0, SS_OK
	bl	PrintWord
/*
@	mov	r0, pc
@	bl	PrintHexWord	@dont't know why this is unavailable.
*/
#endif

#if defined(CONFIG_S3C2410)/*	@jun added*/
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate:				/* relocate U-Boot to RAM	    */
	adr	r0, _start		/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
	cmp     r0, r1                  /* don't reloc during debug         */
	beq     stack_setup

	ldr	r2, _armboot_start
	ldr	r3, _bss_start
	sub	r2, r3, r2		/* r2 <- size of armboot            */
	add	r2, r0, r2		/* r2 <- source end address         */

copy_loop:
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end addreee [r2]    */
	ble	copy_loop
#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
#endif  /*end #if defined(CONFIG_S3C2410)*/

#ifdef CONFIG_S3C2440_NAND_BOOT
#if defined(CONFIG_S3C2440)
        @ Print current Program Counter
        ldr     r1, SerBase
        mov     r0, #'\r'
        bl      PrintChar
        mov     r0, #'\n'
        bl      PrintChar
        mov     r0, #'@'
        bl      PrintChar
	mov     r0, #'2'
        bl      PrintChar
#endif

	@ reset NAND
	mov	r1, #NAND_CTL_BASE
	ldr	r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )
	str	r2, [r1, #oNFCONF]
	ldr	r2, [r1, #oNFCONF]
	
	ldr	r2, =( (1<<4)|(0<<1)|(1<<0) )	@ Active low CE Control 
	str	r2, [r1, #oNFCONT]
	ldr	r2, [r1, #oNFCONT]
	
	ldr	r2, =(0x6)	@ RnB Clear
	str	r2, [r1, #oNFSTAT]
	ldr	r2, [r1, #oNFSTAT]
	
	mov	r2, #0xff	@ RESET command
	strb	r2, [r1, #oNFCMD]
	
	mov	r3, #0	@ wait
nand1: 
	add	r3, r3, #0x1
	cmp	r3, #0xa
	blt	nand1

nand2:
	ldr	r2, [r1, #oNFSTAT]	@ wait ready
	tst	r2, #0x4
	beq	nand2
	
	
	ldr	r2, [r1, #oNFCONT]
	orr	r2, r2, #0x2	@ Flash Memory Chip Disable
	str	r2, [r1, #oNFCONT]
	
	@ get read to call C functions (for nand_read())
	ldr	sp, DW_STACK_START	@ setup stack pointer
	mov	fp, #0	@ no previous frame, so fp=0
/*jUN*/	
#if defined(CONFIG_UTU2440_DEBUG_LED)
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_F		/*light1*/
	mov	r2, #0xe0
	str	r2, [r1, #oGPIO_DAT]

#endif	/*end CONFIG_UTU2440_DEBUG_LED*/


	@ copy U-Boot to RAM
	ldr	r0, =TEXT_BASE	@RAM: buffer addr
	mov	r1, #0x0	@source addr
	mov	r2, #0x30000
	bl	nand_read_ll
	tst	r0, #0x0
	beq	ok_nand_read

bad_nand_read:
loop2:
	b	loop2	@ infinite loop

ok_nand_read:
#if defined(CONFIG_UTU2440_DEBUG_LED)
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_F		/*light2*/
	mov	r2, #0xd0
	str	r2, [r1, #oGPIO_DAT]


        ldr     r1, SerBase
        mov     r0, #'\r'
        bl      PrintChar
        mov     r0, #'\n'
        bl      PrintChar
        mov     r0, #'@'
        bl      PrintChar
	mov     r0, #'3'
        bl      PrintChar

@	ldr     r0, =0xffffff35
@	bl	PrintHexWord
@	mov	r0, pc
@	bl	PrintHexWord

@print
@	ldr	r0, SS_OK
@	ldr	r1, SerBase
@	bl	PrintWord
#endif @end CONFIG_UTU2440_DEBUG_LED
	@ verify
	mov	r0, #0
	ldr	r1, =TEXT_BASE
	mov	r2, #0x400	@ 4 bytes * 1024 = 4K-bytes, stepping alone.
go_next:
	ldr	r3, [r0], #4
	ldr	r4, [r1], #4
	teq	r3, r4
	bne	notmatch
	subs	r2, r2, #4
	beq	stack_setup
	bne	go_next

notmatch:
loop3:
	b	loop3	@ infinite loop
#endif


	/* Set up the stack						    */
stack_setup:
	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

clear_bss:
	ldr	r0, _bss_start		/* find start of bss segment        */
	ldr	r1, _bss_end		/* stop here                        */
	mov 	r2, #0x00000000		/* clear                            */

clbss_l:str	r2, [r0]		/* clear loop...                    */
	add	r0, r0, #4
	cmp	r0, r1
	ble	clbss_l

#if 0
	/* try doing this stuff after the relocation */
	ldr     r0, =pWTCON
	mov     r1, #0x0
	str     r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */