utu2440.h

移植好的杨创utu2440F ARM9 的uboot1.1.4代码

#define rNFDATA          (*(volatile unsigned char*)0x4e000010)
#define rNFSTAT          (*(volatile unsigned int*)0x4e000020)
#define rNFECC           (*(volatile unsigned int*)0x4e00002c)

/*-----------------------------------------------------------------------
//DRAM
*/
#define vREFRESH_406_148        0x00aC03F4
#define cpu_406_148
/* some set add by lili 2006-12-16*/
#ifdef	cpu_406_136d
#define UART_PCLK           UART_PCLK_406_136d
#define vMPLLCON_NOW_USER ((MDIV_406_136d << 12) | (PDIV_406_136d << 4) | (SDIV_406_136d))
#define vCLKDIVN_NOW        CLKDVIN_406_136d
#define vREFRESH            vREFRESH_406_136d
#endif
#ifdef	cpu_406_148
#define vREFRESH            vREFRESH_406_148
#endif

#define vBWSCON			0x22111110
#define vBANKCON0		0x00000700
#define vBANKCON1		0x00000700
#define vBANKCON2		0x00000700
#define vBANKCON3		0x00000700
#define vBANKCON4		0x00000700
#define vBANKCON5		0x00000700
#define vBANKCON6		0x00018009
#define vBANKCON7		0x00018009
#define vBANKSIZE		0xB2
#define vMRSRB6			0x30
#define vMRSRB7			0x30
#define vLOCKTIME		0x00ffffff	/* It's a default value */
#define vCLKCON			0x0000fff8	/* It's a default value */

#define MEM_CTL_BASE		0x48000000
#define bMEMCTL(Nb)		__REGl(MEM_CTL_BASE + (Nb))
#define oBWSCON			0x00	/* R/W, Bus width and wait status ctrl reg. */
#define oBANKCON0		0x04	/* R/W, Bank 0 control reg. */
#define oBANKCON1		0x08	/* R/W, Bank 1 control reg. */
#define oBANKCON2		0x0C	/* R/W, Bank 2 control reg. */
#define oBANKCON3		0x10	/* R/W, Bank 3 control reg. */
#define oBANKCON4		0x14	/* R/W, Bank 4 control reg. */
#define oBANKCON5		0x18	/* R/W, Bank 5 control reg. */
#define oBANKCON6		0x1C	/* R/W, Bank 6 control reg. */
#define oBANKCON7		0x20	/* R/W, Bank 7 control reg. */
#define oREFRESH		0x24	/* R/W, SDRAM refresh control register */
#define oBANKSIZE		0x28	/* R/W, Flexible bank size register */
#define oMRSRB6			0x2C	/* R/W, Mode register set register bank 6 */
#define oMRSRB7			0x2C	/* R/W, Mode register set register bank 7 */


/*-----------------------------------------------------------------------
GPIO
*/
/* GPIO */
#define GPIO_CTL_BASE           0x56000000
#define bGPIO(p,o)              __REGl(GPIO_CTL_BASE + (p) + (o))
/* Offset */
#define oGPIO_CON               0x0     /* R/W, Configures the pins of the port */
#define oGPIO_DAT               0x4     /* R/W, Data register for port */
#define oGPIO_UP                0x8     /* R/W, Pull-up disable register */
#define oGPIO_RESERVED          0xC     /* R/W, Reserved */
#define oGPIO_A                 0x00
#define oGPIO_B                 0x10
#define oGPIO_C                 0x20
#define oGPIO_D                 0x30
#define oGPIO_E                 0x40
#define oGPIO_F                 0x50
#define oGPIO_G                 0x60
#define oGPIO_H                 0x70
#define oMISCCR                 0x80    /* R/W, Miscellaneous control register */

/*-----------------------------------------------------------------------
 UART
 */
#define UART_CTL_BASE           0x50000000
#define UART0_CTL_BASE          UART_CTL_BASE
#define UART1_CTL_BASE          UART_CTL_BASE + 0x4000
#define UART2_CTL_BASE          UART_CTL_BASE + 0x8000
#define bUART(x, Nb)            __REGl(UART_CTL_BASE + (x)*0x4000 + (Nb))
#define bUARTb(x, Nb)           __REGb(UART_CTL_BASE + (x)*0x4000 + (Nb))
/* Offset */
#define oULCON                  0x00    /* R/W, UART line control register */
#define oUCON                   0x04    /* R/W, UART control register */
#define oUFCON                  0x08    /* R/W, UART FIFO control register */
#define oUMCON                  0x0C    /* R/W, UART modem control register */
#define oUTRSTAT                0x10    /* R  , UART Tx/Rx status register */
#define oUERSTAT                0x14    /* R  , UART Rx error status register */
#define oUFSTAT                 0x18    /* R  , UART FIFO status register */
#define oUMSTAT                 0x1C    /* R  , UART Modem status register */
#define oUTXHL                  0x20    /*   W, UART transmit(little-end) buffer */
#define oUTXHB                  0x23    /*   W, UART transmit(big-end) buffer */
#define oURXHL                  0x24    /* R  , UART receive(little-end) buffer */
#define oURXHB                  0x27    /* R  , UART receive(big-end) */

#define oUBRDIV                 0x28    /* R/W, Baud rate divisor register */
/* Registers */
#define ULCON0                  bUART(0, oULCON)
#define UCON0                   bUART(0, oUCON)
#define UFCON0                  bUART(0, oUFCON)
#define UMCON0                  bUART(0, oUMCON)
#define UTRSTAT0                bUART(0, oUTRSTAT)
#define UERSTAT0                bUART(0, oUERSTAT)
#define UFSTAT0                 bUART(0, oUFSTAT)
#define UMSTAT0                 bUART(0, oUMSTAT)
#define UTXH0                   bUARTb(0, oUTXHL)
#define URXH0                   bUARTb(0, oURXHL)
#define UBRDIV0                 bUART(0, oUBRDIV)
#define ULCON1                  bUART(1, oULCON)
#define UCON1                   bUART(1, oUCON)
#define UFCON1                  bUART(1, oUFCON)
#define UMCON1                  bUART(1, oUMCON)
#define UTRSTAT1                bUART(1, oUTRSTAT)
#define UERSTAT1                bUART(1, oUERSTAT)

#define UFSTAT1                 bUART(1, oUFSTAT)
#define UMSTAT1                 bUART(1, oUMSTAT)
#define UTXH1                   bUARTb(1, oUTXHL)
#define URXH1                   bUARTb(1, oURXHL)
#define UBRDIV1                 bUART(1, oUBRDIV)
#define ULCON2                  bUART(2, oULCON)
#define UCON2                   bUART(2, oUCON)
#define UFCON2                  bUART(2, oUFCON)
#define UMCON2                  bUART(2, oUMCON)
#define UTRSTAT2                bUART(2, oUTRSTAT)
#define UERSTAT2                bUART(2, oUERSTAT)
#define UFSTAT2                 bUART(2, oUFSTAT)
#define UMSTAT2                 bUART(2, oUMSTAT)
#define UTXH2                   bUARTb(2, oUTXHL)
#define URXH2                   bUARTb(2, oURXHL)
#define UBRDIV2                 bUART(2, oUBRDIV)
#define UTRSTAT_TX_EMPTY (1<<2)
#define UTRSTAT_RX_EMPTY (1<<0)

//~jun
#define UART_PCLK  50625000
#define UART_BAUD_RATE 115200
/*-----------------------------------------------------------------------
//
*/

#define CONFIG_CMD_NAND
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_JFFS2
/* JFFS2 Support    080218  */
#define CONFIG_CMD_USB
/* USB Support  080218  */
#define CONFIG_CMD_FAT
/* FAT support  080218  */



/*-----------------------------------------------------------------------
//
*/
//JFFS2
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_NAND 1
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_JFFS2_PART_SIZE 0X4C0000
#define CONFIG_JFFS2_PART_OFFSET 0X40000

//USB
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#define CONFIG_USB_KEYBOARD
#define CONFIG_DOS_PARTITION
#define CFG_DEVICE_DEREGISTER
#define CONFIG_SUPPORT_VFAT
#define LITTLEENDIAN
#endif //end CONFIG_S3C2440
//~JUN

//Jun
#define	CFG_ENV_IS_IN_NAND 1
#define   CFG_ENV_OFFSET 		0X30000
#define   CFG_NAND_LEGACY
/*----------------------------------------------------------------------
 * NAND flash settings
 */
#if defined(CFG_CMD_NAND)
#define CFG_NAND_BASE 0x4E000000 
/* NandFlash控制器在SFR区起始寄存器地址 */
#define CFG_MAX_NAND_DEVICE 1
 /* 支持的最在Nand Flash数据 */
#define SECTORSIZE 512 
/* 1页的大小 */
#define NAND_SECTOR_SIZE SECTORSIZE
#define NAND_BLOCK_MASK 511
/* 页掩码 */
#define ADDR_COLUMN 1 
/* 一个字节的Column地址 */ 
#define ADDR_PAGE 3 
/* 3字节的页块地址!!!!!*/
#define ADDR_COLUMN_PAGE 4 
/* 总共4字节的页块地址!!!!! */
#define NAND_ChipID_UNKNOWN 0x00 
/* 未知芯片的ID号 */
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
/* Nand Flash命令层底层接口函数 */
#define WRITE_NAND_ADDRESS(d, adr) {rNFADDR = d;}
#define WRITE_NAND(d, adr) {rNFDATA = d;}
#define READ_NAND(adr) (rNFDATA)
#define NAND_WAIT_READY(nand) {while(!(rNFSTAT&(1<<0)));}
#define WRITE_NAND_COMMAND(d, adr) {rNFCMD = d;}
#define WRITE_NAND_COMMANDW(d, adr)    NF_CmdW(d)

#if defined(CONFIG_S3C2440)
#define NAND_DISABLE_CE(nand) {rNFCONT |= (1<<1);}
#define NAND_ENABLE_CE(nand) {rNFCONT &= ~(1<<1);}
#else	//for 2410
#define NAND_DISABLE_CE(nand) {rNFCONF |= (1<<11);}
#define NAND_ENABLE_CE(nand) {rNFCONF &= ~(1<<11);}
#endif

/* the following functions are NOP's because S3C24X0 handles this in hardware */

#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
/* 允许Nand Flash写校验 */
#define CONFIG_MTD_NAND_VERIFY_WRITE 1

#endif //#if defined(CFG_CMD_NAND)
//~JUN

/*
#define CONFIG_EXTRA_ENV_SETTINGS                       \
	"updater=dhcp;tftp 1100000 $(path)$(updaterfile);"	\
        "bootm 1100000\0"	                            \
        ""
*/

#endif	/* __CONFIG_H */