idt_512kx18_pbsram_test.v

memory control source code

  $display($time,,"Byte mode read/write test - random data");
//  GW_ = 1;                        // Disable global write
//  BWE_  = 0;                      // Enable byte write
  for (i=0;i<`Max;i=i+1) begin    // Test byte write/read
    BW_ = $random;
    TempReg = RandomData[i];
    byte_write_random(i, TempReg);
    if ( BW_[1] == 1 ) TempReg[8:0] = 0;
    if ( BW_[2] == 1 ) TempReg[17:9] = 0;
    read_random(i, DataOut, TempReg);
  end
  BWE_  = 1;                      // Disable byte write


  // Test burst mode write/read
  $display($time,,"Burst mode read/write test - random data");
  for (i=0;i<`Max;i=i+1) begin      // Test byte write/read
      BurstData[i] = RandomData[i];
  end

  GW_ = 0;                       // Enable global write
  for (i=0;i<`Max;i=i+4) begin   // Write data from BurstData buffer
    burst_write_random(i,4); 
  end
  GW_ = 1;                       // Disable global write

  for (i=0;j<`Max;i=i+1) begin   // Clear data buffer
      BurstData[i] = 0;
  end
  
  for (i=0;i<`Max;i=i+4) begin
    burst_read_random(i,4); 
//    for (j=i;j<i+4;j=j+1) begin      // verify read data
//      if ( BurstData[j] != RandomData[j] )
//          $display("%d  Burst error: Addr %h Exp %h Act %h", $stime, j, RandomData[j], BurstData[j]);
//    end
  end
  burst_wrap_random(0);
  disable_ce;
  burst_rd_pipe_random(0,4);

  $finish;
end
/////////////////////////////////////////////////////////////////

always @(posedge CLK) begin
   if ((~ADSC_ | ~ADSP_) & ~CE_ & CS0 & ~CS1_) qual_ads <= #1 1;
   else qual_ads <= #1 0;
   check_data_m1 <= #1 ~ADV_;

   if (pipe == 0) check_data = #1 (qual_ads | ~ADV_);
   else check_data = #1 (qual_ads | check_data_m1);
end

always #(Tcyc/2) CLK = ~CLK;

`device  dut (
    .A        (A), 
    .D        (DQbus), 
    .DP       (DQPbus), 
    .oe_      (OE_),
    .ce_      (CE_),
    .cs0      (CS0),
    .cs1_     (CS1_),
    .lbo_     (LBO_),
    .gw_      (GW_),
    .bwe_     (BWE_),
    .bw2_     (BW_[2]),
    .bw1_     (BW_[1]),
    .adsp_    (ADSP_),
    .adsc_    (ADSC_),
    .adv_     (ADV_),
    .clk      (CLK)
    );

//================ test bench tasks

task disable_ce;
begin
    OE_ = 0;
    if (CLK)
        @( negedge CLK );
    ADSC_ = 0;
    CE_   = 1;
    @( posedge CLK );
    @( negedge CLK );
    ADSC_ = 1;
    CE_   = 0;
end
endtask

task disable_cs0;
begin
    OE_ = 0;
    if (CLK)
        @( negedge CLK );
    ADSP_ = 0;
    CS0   = 0;
    @( posedge CLK );
    @( negedge CLK );
    ADSP_ = 1;
    CS0   = 1;
end
endtask

task dummy_cyc;
input oe;
begin
@(posedge CLK);
  @(negedge CLK);
   #Tcd;
   OE_ = oe;
end
endtask

task init;
begin
  for(i=0; i<`Max2; i=i+1) begin         // fill memory with 0 data
    write(i,0,0,1,0,0,0,1);              // addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
    Dstore[i] = 18'hx;                   // fill temp memory with xx data
  end
end
endtask

task read;                   // ADSP|ADSC controlled PL - adsp_/adsc_ 2cycle read
input  [addr_msb:0] addr;    // ADSP|ADSC controlled FT - adsp_/adsc_ 1cycle read
input  adsp_;
input  adsc_;
input  ce_; 
input  cs1_;
input  cs0; 
begin
   @( negedge CLK );
    #(Tcyc/2 - Tsu);
    A     = addr;
    ADV_  = 1;
    GW_   = 1;
    BWE_  = 1;
    ADSP_ = adsp_;
    ADSC_ = adsc_;
    CE_   = ce_;
    CS1_  = cs1_;
    CS0   = cs0;
      assign data = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
   @( posedge CLK );           // SRAM latches Address and begins internal read
     tempcs0  <= cs0; tempcs1_  <= cs1_; tempce_  <= ce_;
     lastaddr <= addr;
     A <= #Tdh 19'hz;
     ADSP_ <= #Tdh 1;
     ADSC_ <= #Tdh 1;
     CE_ <= #Tdh 1;
     CS1_<= #Tdh 1;
     CS0 <= #Tdh 0;
     if(pipe == 1)
       OE_ <= #(Tcyc+Tcd-Toe) 0;
     else if(pipe == 0) 
       OE_ <= #(Tcd-Toe) 0;
     if(counter != 0)
       if ( data !== Dstore[lastaddr] ) begin
         if (tempcs0 & ~tempce_ & ~tempcs1_) begin
         status = "FAIL";
            $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                      Dstore[lastaddr], data);
         end
         end
       else if (tempcs0 & ~tempce_ & ~tempcs1_)
               status = "PASS";
    DQ = 18'hz;
    if(pipe == 1)
      #(Tcyc/2);
    counter = counter+1;
end
endtask

task burst_read;             // ADSP|ADSC controlled - adsp/adsc 3-1-1-1 PL read
input  [addr_msb:0] addr;    //                        adsp/adsc 2-1-1-1 FT read
input  adsp_;
input  adsc_;
input  ce_; 
input  cs1_;
input  cs0; 
input  [3:0] nburst;
integer tempaddr,tempcounter;
begin
tempcounter = 0;
 for (tempaddr=addr; tempaddr<addr+nburst; tempaddr=tempaddr+1) begin
   @( negedge CLK );
   if (tempaddr == addr) begin           // 1st address
      #(Tcyc/2 - Tsu);
      A     = addr;
      GW_   = 1;
      BWE_  = 1;
      ADSP_ = adsp_;
      ADSC_ = adsc_;
      ADV_  = 1;
      CE_   = ce_;
      CS1_  = cs1_;
      CS0   = cs0;
   end
   else begin
      #(Tcyc/2 - Tsu);                  // after 2nd address
      A     = 19'hz;
      ADV_ = 0;  
   end
    assign data = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
   @( posedge CLK );      // SRAM latches Address and begins internal read
   lastaddr <= #(Tcyc) tempaddr;
   if (tempaddr == addr) begin           // 1st address
      A <= #Tdh 19'hz;
      ADSP_ <= #Tdh 1;
      ADSC_ <= #Tdh 1;
      CE_   <= #Tdh ~ce_;
      CS1_  <= #Tdh ~cs1_;
      CS0   <= #Tdh ~cs0;
      if(pipe == 1)
        OE_ <= #(Tcyc+Tcd-Toe) 0;
      if(pipe == 0)
        OE_ <= #(Tcd-Toe) 0;
   end
   else begin                            // after 2nd address
      ADV_  <= #Tdh 1;
   end
      if(pipe == 1)
        if(tempcounter > 1 )
          if ( data !== Dstore[lastaddr] ) begin
               status = "FAIL";
               $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                         Dstore[lastaddr], data);
          end
          else status = "PASS";
      else if(pipe == 0)
        if(tempcounter > 0 )
          if ( data !== Dstore[lastaddr] ) begin
               status = "FAIL";
               $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                         Dstore[lastaddr], data);
          end
          else status = "PASS";
    DQ = 18'hz;
    #Tdh;
    tempcounter = tempcounter+1;
 end
end
endtask

task burst_read_adv;       // ADSP|ADSC controlled - adsp/adsc 3-1-1-1 PL read
input  [addr_msb:0] addr;        //                        adsp/adsc 2-1-1-1 FT read
input  adsp_;
input  adsc_;
input  ce_; 
input  cs1_;
input  cs0; 
input  adv_;
input  [3:0] tempcounter;
begin
   @( negedge CLK );
   if (tempcounter == 0) begin            // 1st address
      #(Tcyc/2 - Tsu);
      A     = addr;
      GW_   = 1;
      BWE_  = 1;
      ADSP_ = adsp_;
      ADSC_ = adsc_;
      ADV_  = adv_;
      CE_   = ce_;
      CS1_  = cs1_;
      CS0   = cs0;
   end
   else begin
      #(Tcyc/2 - Tsu);                  // after 2nd address
      A     = 19'hz;
      ADSP_ = adsp_;
      ADSC_ = adsc_;
      CE_   = ce_;
      ADV_ = adv_;  
   end
    assign data = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
   @( posedge CLK );      // SRAM latches Address and begins internal read
   lastaddr <= #(Tcyc) addr;
   if (tempcounter == 0) begin           // 1st address
      A <= #Tdh 19'hz;
      ADSP_ <= #Tdh ~adsp_;
      ADSC_ <= #Tdh ~adsc_;
      CE_   <= #Tdh ~ce_;
      CS1_  <= #Tdh ~cs1_;
      CS0   <= #Tdh ~cs0;
      if(pipe == 1)
        OE_ <= #(Tcyc+Tcd-Toe) 0;
      if(pipe == 0)
        OE_ <= #(Tcd-Toe) 0;
   end
   else begin                            // after 2nd address
      ADSP_ <= #Tdh ~adsp_;
      ADSC_ <= #Tdh ~adsc_;
      CE_   <= #Tdh ~ce_;
      ADV_  <= #Tdh ~adv_;
   end
      if(pipe == 1)
        if(tempcounter > 1 )
          if ( data !== Dstore[lastaddr] ) begin
               status = "FAIL";
               $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                         Dstore[lastaddr], data);
          end
          else status = "PASS";
      else if(pipe == 0)
        if(tempcounter > 0 )
          if ( data !== Dstore[lastaddr] ) begin
               status = "FAIL";
               $display("%d Read error: Addr %h Exp %h Act %h", $stime, lastaddr, 
                         Dstore[lastaddr], data);
          end
          else status = "PASS";
    DQ = 18'hz;
end
endtask

task read_random;
input  [addr_msb:0] addr;
output [17:0] data;
input  [17:0] exp;
begin
    if (CLK )
        @( negedge CLK );
//    DQ = 18'hz;
    ADV_  = 1;
    A = addr;
    ADSP_ = 0;
    @( posedge CLK );      // SRAM latches Address and begins internal read
    @( negedge CLK );
    ADSP_ = 1;
    OE_   = 0;
    if (pipe == 1) @( posedge CLK );      // SRAM begins placing data onto bus
    @( posedge CLK );      // Data sampled by reading device
                           // Hopefully the SRAM has an output hold time
    data = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
    if ( data !== exp )
        $display("%d Read_random error: Addr %h Exp %h Act %h", $stime, addr, exp, data);
    @( negedge CLK ); 
    OE_   = 1;

end
endtask

task burst_read_random;   
input  [addr_msb:0] addr;
input  [17:0] n;
integer       i;
begin
    DQ = 18'hz;
    if ( CLK )
        @( negedge CLK );
    #1 A = addr;
       ADSP_ = 0;
    @( posedge CLK );           // Address latched by SRAM, begins internal read
    #(Tcyc/2) ADSP_ = 1;       // SRAM starts driving bus (flow-through)
    #1 OE_   = 0;
       ADV_  = 0;
    if (pipe == 1) @(posedge CLK); //SRAM starts driving bus (pipelined)
 
    for (i=addr;i<addr+n;i=i) begin
       @( posedge CLK ) begin
          if (check_data == 1) 
BurstData[i] = {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]};
          if ( BurstData[i] !== RandomData[i] && check_data == 1 )
             $display("%d task burst_read_random read error: Addr %h Exp %h Act %h", $stime, i, RandomData[i], BurstData[i]);
       end
       @( negedge CLK );