idt_512kx18_pbsram_test.v

memory control source code

///////////////////////////////////////////////////////////
//
//    Test fixture for IDT 9Meg Synchronous Burst SRAMs
//              (for 512K x 18 configurations)
//
//////////////////////////////////////////////////////////

`timescale 1ns / 10ps

`define Max 16
`define Max1 8
`define Max2 16

module main;

parameter addr_msb = 18;


/////// Remove comments for specific device under test ////


//////////////////////////////////////////////
//
//Pipelined sync burst SRAMs
//
/////////////////////////////////////////////

/////// 2.5v I/O ////////////
parameter pipe = 1, Tcyc = 7.5, Tsu = 1.5, Tdh = 0.5, Tcd = 4.2, Toe = 4.2; 
          `define device idt71t67802s133
//parameter pipe = 1, Tcyc = 6.7, Tsu = 1.5, Tdh = 0.5, Tcd = 3.8, Toe = 3.8; 
//          `define device idt71t67802s150
//parameter pipe = 1, Tcyc = 6.0, Tsu = 1.5, Tdh = 0.5, Tcd = 3.5, Toe = 3.5; 
//          `define device idt71t67802s166

//////////////////////////////////////////////
//
//Flow-through sync burst SRAMs
//
//////////////////////////////////////////////

/////// 2.5v I/O ////////////
//parameter pipe = 0, Tcyc = 11.5, Tsu = 2.0, Tdh = 0.5, Tcd = 8.5, Toe = 3.5; 
//          `define device idt71t67902s85
//parameter pipe = 0, Tcyc = 10.0, Tsu = 2.0, Tdh = 0.5, Tcd = 8.0, Toe = 3.5; 
//          `define device idt71t67902s80
//parameter pipe = 0, Tcyc = 8.5,  Tsu = 1.5, Tdh = 0.5, Tcd = 7.5, Toe = 3.5; 
//          `define device idt71t67902s75

reg   [addr_msb:0] A;
reg          CLK;
reg          ADSP_;
reg          ADV_;
reg          LBO_;
reg          ADSC_;
reg    [2:1] BW_;
reg          BWE_;
reg          GW_;
reg          CE_;
reg          CS0;
reg          CS1_;
reg          OE_;

reg   [17:0] DataOut;
reg   [17:0] TempReg;

reg   [17:0] DQ;
wire  [15:0] DQbus = {DQ[16:9], DQ[7:0]};
wire  [2:1]  DQPbus = {DQ[17], DQ[8]};
reg   [17:0] Dstore[0:`Max-1];              //temp data store
reg   [17:0] data;
reg   [addr_msb:0] lastaddr;
reg          tempcs1_;
reg          tempcs0;
reg          tempce_;

reg   [17:0] RandomData[0:`Max-1];
reg   [17:0] BurstData[0:`Max-1];

reg  [8*4:1] status;                       //data read pass/fail

//internal

reg check_data_m1, qual_ads;
reg check_data;

integer   i,j,addrb,counter,
          result;

// Output files
initial begin
  $recordfile ("idt_sram_67802.trn");
  $recordvars;

//  $dumpfile ("idt_sram_67802.vcd");
//  $dumpvars;

  result = $fopen("idt_sram.res"); if (result == 0) $finish;
end

always begin
  @(posedge CLK) 
    $fdisplay(result,
      "%b",  ADSC_,
      "%b",  ADSP_,
      "%b",  BWE_,
      "%b",  CE_,
      "%b",  CS0,
      "%b",  CS1_,
      "%b",  LBO_,
      "%b",  OE_,
      "%b",  BW_,  // 2 bits
      "%b",  ADV_,
      "%b ", GW_,
      "%h ", {DQPbus[2], DQbus[15:8], DQPbus[1], DQbus[7:0]},
      "%h ", A,
      "%d", $stime
      );
end

initial begin
  ADSC_ = 1;
  ADSP_ = 1;
  BWE_  = 1;
  CE_   = 0;
  CS0   = 1;
  CS1_  = 0;
  LBO_  = 0;
  OE_   = 1;
  CLK   = 0;
  BW_   = 2'hf;
  ADV_  = 1;
  GW_   = 1;
  counter = 0;

  for (i=0;i<`Max;i=i+1) begin           // Generate random data for testing
    RandomData[i] = $random;
  end

//****************
//disable_ce;
//disable_cs0;

//####
init;
$display($time,"(1)  write        adsp_ = 0");
for(i=0; i<`Max1; i=i+1) begin
write(i,i,0,1,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
end
$display($time,"     read         adsp_ = 0");
for(i=0; i<`Max1; i=i+1) begin
read(i,0,1,0,0,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
end
dummy_cyc(1);
$display($time,"                  status = %s",status);
 
//####
init;
$display($time,"(2)  write        adsc_ = 0");
for(i=0; i<`Max1; i=i+1) begin
write(i,i,1,0,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
end
$display($time,"     read         adsc_ = 0");
for(i=0; i<`Max1; i=i+1) begin
read(i,1,0,0,0,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(3)  write        adsp_ = 0");
for(i=0; i<`Max1; i=i+1) begin
write(i,i,0,1,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
end
$display($time,"     read         adsp_ = 0 cs1_ = 1 - every other cyc");
for(i=0; i<`Max1; i=i+2) begin
read(i,0,1,0,1,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
read(i+1,0,1,0,0,1);                     //addr,adsp_,adsc_,ce_,cs1_,cs0
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(4)  write/read   adsp_ = 0");
for(i=0; i<`Max1; i=i+1) begin
write(i,i,0,1,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
read(i,0,1,0,0,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(5)  write/read   adsc_ = 0");
for(i=0; i<`Max1; i=i+1) begin
write(i,i,1,0,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
read(i,1,0,0,0,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
dummy_cyc(1);
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(6)  burst_write  adsp_ = 0");
for(i=0; i<`Max2; i=i+4) begin
burst_write(i,i,0,1,0,0,0,1,4);          //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0,nburst
end
$display($time,"     burst_read   adsp_ = 0");
for(i=0; i<`Max2; i=i+4) begin
burst_read(i,0,1,0,0,1,4);               //addr,adsp_,adsc_,ce_,cs1_,cs0,nburst
end
dummy_cyc(1);
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(7)  burst_write  adsc_ = 0");
for(i=0; i<`Max2; i=i+4) begin
burst_write(i,i,1,0,0,0,0,1,4);          //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0,nburst
end
$display($time,"     burst_read   adsc_ = 0");
for(i=0; i<`Max2; i=i+4) begin
burst_read(i,1,0,0,0,1,4);               //addr,adsp_,adsc_,ce_,cs1_,cs0,nburst
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(8)  write        adsp_ = 0 cs1_ = 1 - every other cyc");
for(i=0; i<`Max1; i=i+2) begin
write(i,i,0,1,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
write(i+1,9,0,1,0,0,1,1);                //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
end
$display($time,"     read         adsp_ = 0");
for(i=0; i<`Max1; i=i+2) begin
read(i,0,1,0,0,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(9)  write        adsp_ = 0 cs0  = 0 - every other cyc");
for(i=0; i<`Max1; i=i+2) begin
write(i,i,0,1,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
write(i+1,9,0,1,0,0,0,0);                //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
end
$display($time,"     read         adsc_ = 0");
for(i=0; i<`Max1; i=i+2) begin
read(i,1,0,0,0,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(10) write        adsp_ = 0 ce_  = 1 - every other cyc");
for(i=0; i<`Max1; i=i+2) begin
write(i,i,0,1,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
write(i+1,i,0,1,0,1,0,1);                //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
end
write(i,i,0,1,0,0,0,1);                  //this will write last address to Dstore
$display($time,"     read         adsp_ = 0");
for(i=0; i<`Max1; i=i+2) begin
read(i,0,1,0,0,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(11) write        adsc_ = 0 ce_  = 1 - every other cyc");
for(i=0; i<`Max1; i=i+2) begin
write(i,i,1,0,0,0,0,1);                  //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
write(i+1,i+1,1,0,0,1,0,1);              //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0
end
write(i,i,1,0,0,0,0,1);                  //this will write last address to Dstore
$display($time,"     read         adsc_ = 0");
for(i=0; i<`Max1; i=i+2) begin
read(i,1,0,0,0,1);                       //addr,adsp_,adsc_,ce_,cs1_,cs0
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(12) burst_write_adv  adsc_ = 0 adv_ = 1 - 2nd cyc");
for(i=0; i<`Max2; i=i+4) begin
burst_write_adv(i,i,1,0,0,0,0,1,1,0);     //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0,adv_,tempcounter
burst_write_adv(i,i,1,0,0,0,0,1,1,1);     
burst_write_adv(i+1,i+1,1,0,0,0,0,1,0,2); 
burst_write_adv(i+2,i+2,1,0,0,0,0,1,0,3); 
burst_write_adv(i+3,i+3,1,0,0,0,0,1,0,4); 
end
$display($time,"     burst_read   adsc_ = 0");
for(i=0; i<`Max2; i=i+4) begin
burst_read(i,1,0,0,0,1,4);               //addr,adsp_,adsc_,ce_,cs1_,cs0,nburst
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(13) burst_write_adv  adsp_ = 0 adv_ = 1 - 2nd cyc");
for(i=0; i<`Max2; i=i+4) begin
burst_write_adv(i,i,0,1,0,0,0,1,1,0);     //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0,adv_,tempcounter
burst_write_adv(i,i,0,0,0,1,0,1,1,1);     
burst_write_adv(i+1,i+1,0,1,0,0,0,1,0,2); 
burst_write_adv(i+2,i+2,0,1,0,0,0,1,0,3); 
burst_write_adv(i+3,i+3,0,1,0,0,0,1,0,4); 
end
$display($time,"     burst_read   adsc_ = 0");
for(i=0; i<`Max2; i=i+4) begin
burst_read(i,1,0,0,0,1,4);               //addr,adsp_,adsc_,ce_,cs1_,cs0,nburst
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(14) burst_write  adsp_ = 0");
for(i=0; i<`Max2; i=i+4) begin
burst_write(i,i,0,1,0,0,0,1,4);          //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0,nburst
end
$display($time,"     burst_read_adv   adsp_ = 0 adv_ = 1 - 3rd cyc");
for(i=0; i<`Max2; i=i+4) begin
burst_read_adv(i,  0,1,0,0,1,1,0);       //addr,adsp_,adsc_,ce_,cs1_,cs0,adv_,tempcounter
burst_read_adv(i+1,1,1,0,0,1,0,1);       
burst_read_adv(i+2,1,1,0,0,1,1,2);      
burst_read_adv(i+3,1,1,0,0,1,0,3);     
end
$display($time,"                  status = %s",status);

//####
init;
$display($time,"(15) burst_write  adsp_ = 0");
for(i=0; i<`Max2; i=i+4) begin
burst_write(i,i,0,1,0,0,0,1,4);          //addr,data,adsp_,adsc_,gw_,ce_,cs1_,cs0,nburst
end
$display($time,"     burst_read_adv   adsp_=1/ce_=0 - 2/3 cyc, adsp = 0/ce_=1 - 4/5 cyc");
for(i=0; i<`Max2; i=i+4) begin
burst_read_adv(i,  0,1,0,0,1,1,0);       //addr,adsp_,adsc_,ce_,cs1_,cs0,adv_,tempcounter
burst_read_adv(i+1,1,1,0,0,1,0,1);       
burst_read_adv(i+2,1,1,0,0,1,0,2);       
burst_read_adv(i+3,0,1,1,0,1,0,3);       
burst_read_adv(i,  0,1,1,0,1,0,4);       
end
$display($time,"                  status = %s",status);
//####


@( negedge CLK );
@( negedge CLK );
@( negedge CLK );

//*****************
CE_ = 0;
CS0 = 1;
CS1_ = 0;

  $display($time,,"Simple read/write test");
  for (i=0;i<`Max;i=i+1) begin      // Test straight write/read
    write_random(i, RandomData[i]);
  $display($time,,"Simple read test");
    read_random(i, DataOut, RandomData[i]);
  end

 $display($time,,"CE_ disable - random data");
 read_random(3, DataOut, RandomData[3]);
 disable_ce;
 read_random(7, DataOut, RandomData[7]);
 disable_cs0;
 read_random(2, DataOut, RandomData[2]);
  for (i=0;i<`Max;i=i+1) begin      // Fill RAM with zero's
    write_random(i, 0);
  end