📄 adv_bb.v
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//`timescale 1ns/1ns
//****************************************************************************
// This file contains the paramenters which define the part for the
// Smart 3 Advanced Boot Block memory model (adv_bb.v). The '2.7V Vcc Timing'
// parameters are representative of the 28F160B3-120 operating at 2.7-3.6V Vcc.
// These parameters need to be changed if the 28F160B3-150 operating at
// 2.7-3.6V Vcc is to be modeled. The parameters were taken from the Smart 3
// Advanced Boot Block Flash Memory Family datasheet (Order Number 290580).
// This file must be loaded before the main model, as it contains
// definitions required by the model.
//28F160B3-B
`define BlockFileBegin "f160b3b.bkb" //starting addresses of each block
`define BlockFileEnd "f160b3b.bke" //ending addresses of each block
`define BlockFileType "f160b3b.bkt" //block types
//Available Vcc supported by the device.
`define VccLevels 4 //Bit 0 - 5V, Bit 1 = 3.3V, Bit 2 = 2.7V
`define AddrSize 20 //number of address pins
`define MaxAddr `AddrSize'hFFFFF // device ending address
`define MainArraySize 0:`MaxAddr //array definition in bytes
//include A-1 for 8 bit mode
`define MaxOutputs 16 //number of output pins
`define NumberOfBlocks 39 //number of blocks in the array
`define ID_DeviceCodeB 'h8891 //160B3 Bottom
`define ID_ManufacturerB 'h0089
// Timing parameters. See the data sheet for definition of the parameter.
// Only the WE# controlled write timing parameters are used since their
// respective CE# controlled write timing parameters have the same value.
// The model does not differentiate between the two types of writes.
//2.7V Vcc Timing
// Changed the timings below to represent a "c3" device. --- RU 9/9/99
`define TAVAV_27 110
`define TAVQV_27 110
`define TELQV_27 110
`define TPHQV_27 150
`define TGLQV_27 0.1
`define TELQX_27 0
`define TEHQZ_27 20
`define TGLQX_27 0
`define TGHQZ_27 20
`define TOH_27 0
`define TPHWL_27 150
`define TWLWH_27 70
`define TDVWH_27 60
`define TAVWH_27 70
`define TWHDX_27 0
`define TWHAX_27 0
`define TWHWL_27 30
`define TVPWH_27 200
// The following constants control how long it take an algorithm to run
// to scale all times together (for making simulation run faster
// change the constant later listed as TimerPeriod. The actual delays
// are TimerPeriod*xxx_Time, except for the suspend latency times.
`define TimerPeriod_ 1000 //1 usec = 1000ns requires for
//following times to be accurate
// The typical values given in the datasheet are used.
// reducing the following will reduce simulation time
//2.7V Vcc, 12V Vpp
`define AC_ProgramTime_Word_27_12 8 //usecs
`define AC_EraseTime_Param_27_12 800000 //0.8secs
`define AC_EraseTime_Main_27_12 1100000 //1.1secs
//Latency times are NOT multiplied by TimerPeriod_
`define AC_Program_Suspend_27_12 5000 //5 usecs
`define AC_Erase_Suspend_27_12 10000 //10 usecs
//2.7V Vcc 2.7V Vpp
`define AC_ProgramTime_Word_27_27 22 //usecs
`define AC_EraseTime_Param_27_27 1000000 //1sec
`define AC_EraseTime_Main_27_27 1800000 //1.8secs
//Latency times are NOT multiplied by TimerPeriod_
`define AC_Program_Suspend_27_27 6000 //6 usecs
`define AC_Erase_Suspend_27_27 13000 //13 usecs
//generic defines for readability
`define FALSE 1'b0
`define TRUE 1'b1
`define Word 15:0
`define Byte 7:0
`define VIL 1'b0
`define VIH 1'b1
`define Ready 1'b1
`define Busy 1'b0
// These constants are the actual command codes
`define ClearCSRCmd 8'h50
`define ProgramCmd 8'h10
`define Program2Cmd 8'h40
`define EraseBlockCmd 8'h20
`define ReadArrayCmd 8'hFF
`define ReadCSRCmd 8'h70
`define ReadIDCmd 8'h90
`define SuspendCmd 8'hB0 //Valid for both erase
`define ResumeCmd 8'hD0 //and program suspend
`define ConfirmCmd 8'hD0
`define ReadMode_T 2:0
`define rdARRAY 3'b000
`define rdCSR 3'b011
`define rdID 3'b100
`define Program 2'b00
`define Erase 2'b01
// Cmd_T record
`define Cmd_T 172:0
`define CmdAdd_1 172:153
`define CmdAdd_2 152:133
`define Add 132:113
`define CmdData_1 112:97
`define CmdData_2 96:81
`define Cmd 80:73
`define Count 72:41
`define Time 40:9
`define Confirm 8
`define OpBlock 7:2
`define OpType 1:0
`define CmdData1Fx8 104:97
`define WritePtr_T 1:0
`define NewCmd 2'b01
`define CmdField 2'b10
`define BlockType_T 1:0
`define MainBlock 2'b00
`define LockBlock 2'b01
`define ParamBlock 2'b10
`define Vcc2700 3'b100
`define Vcc3300 3'b010
`define Vcc5000 3'b001
// device specific
//module definition for Intel Advanced Boot Block Flash Memory Family
//
//vpp and vcc are are 32 bit vectors which are treated as unsigned int
//scale for vpp and vcc is millivolts. ie. 0 = 0V, 5000 = 5V
//
module IntelAdvBoot(dq, addr, ceb, oeb, web, rpb, wpb, vpp, vcc);
inout [`MaxOutputs-1:0] dq; //16 outputs
input [`AddrSize-1:0] addr; //address pins.
input ceb, //CE# - chip enable bar
oeb, //OE# - output enable bar
web, //WE# - write enable bar
rpb, //RP# - reset bar, powerdown
wpb; //WP# = write protect bar
input [31:0] vpp, //vpp in millivolts
vcc; //vcc in millivolts
reg [`Word] MainArray[`MainArraySize]; //flash array
// Flag to show that a Cmd has been written
// and needs predecoding
reg CmdValid ;
// This points to where data written to the part will
// go. By default it is to NewCmd. CmdField means the
// chip is waiting on more data for the cmd (ie confirm)
reg [`WritePtr_T] WriteToPtr ;
// Contains the current executing command and all its
// support information.
reg [`Cmd_T] Cmd;
reg [`Cmd_T] Algorithm;
reg [`Cmd_T] SuspendedAlg;
// Output of Data
reg [`Word] ArrayOut ;
// Current output of the Compatible status register
reg [`Word] CSROut ;
// Current output of the ID register
reg [`Word] IDOut ;
// Startup Flag phase
reg StartUpFlag ;
// Global Reset Flag
reg Reset ;
//Vpp Monitoring
reg VppFlag ;
reg VppError ;
reg VppErrFlag ;
reg ClearVppFlag ;
// Internal representation of the CSR SR.1 bit
reg BlockLockStatus;
// Internal representation of the CSR SR.4 bit
reg ProgramError;
// Internal representation of the CSR SR.5 bit
reg EraseError;
// Internal representation of CUI modes
reg [`ReadMode_T] ReadMode ;
// Current value of the CSR
wire [`Byte] CSR ;
// Flag that determines if the chip is driving
// the outputs
reg DriveOutputs ;
// Internal value of the out data. If DriveOutputs
// is active this value will be placed on the
// outputs. -1 == Unknown or XXXX
reg [`MaxOutputs-1:0] InternalOutput ;
// Number of addition writes necessary to
// supply the current command information.
// When it hits zero it goes to Decode
integer DataPtr ;
// Master internal write enable
wire Internal_WE ;
// Master internal output enable
wire Internal_OE ;
wire Internal_OE2 ;
wire Internal_OE3 ;
// Master internal read enable
wire Internal_RE ;
// Master internal boot block write enable
reg InternalBoot_WE ;
wire InternalBoot;
// Internal flag to tell if an algorithm is running
reg ReadyBusy ;
//reg RunningAlgorithm ; *******************************
// Flag to represent if the chip is write suspended
reg WriteSuspended ;
// Flag to represent if the chip is erase suspended
reg EraseSuspended ;
// Flag for if the chip should be suspended
reg Suspend ;
// Variable to hold which algorithm (program or erase)
// is to be suspended
reg [1:0] ToBeSuspended;
// Algorithm Timer
reg TimerClk ;
// Flag to show the running algorithm is done.
reg AlgDone ;
// Number of timer cycles remaining for the
// current algorithm
integer AlgTime;
// Number of timer cycles remaining for erase operation
// when erase suspended and program operation in progress
integer TimeLeft;
// Generic temporary varible
integer LoopCntr ;
reg Other ;
//Block begin and end address
reg [`AddrSize-1:0] BlocksBegin[0:`NumberOfBlocks-1];
reg [`AddrSize-1:0] BlocksEnd[0:`NumberOfBlocks-1];
reg [`BlockType_T] BlocksType[0:`NumberOfBlocks-1];
reg [31:0] BlocksEraseCount[0:`NumberOfBlocks-1];
//************************************************************************
//TIMING VALUES
//************************************************************************
time ToOut ;
time last_addr_time ,curr_addr_time;
time last_oe_time, curr_oe_time;
time last_ce_time, curr_ce_time;
time last_rp_time, curr_rp_time;
time last_ReadMode_time, curr_ReadMode_time ;
time last_Internal_RE_time, curr_Internal_RE_time ;
time last_Internal_WE_time, curr_Internal_WE_time ;
time last_dq_time ,curr_dq_time;
time last_rpb_time, curr_rpb_time ;
time WriteRecovery ;
time TempTime;
time Program_Time_Word;
time Param_Erase_Time;
time Main_Erase_Time;
time Program_Suspend_Time; // latency time
time Erase_Suspend_Time; // latency time
//************************************************************************
//input configuration
parameter
LoadOnPowerup = `FALSE, //load array from file
LoadFileName = "f160b3.dat", //File to load array with
SaveOnPowerdown = `FALSE, //save array to file
SaveFileName = "f160b3.dat"; //save file name
//TIMING PARAMETERS
parameter
TAVAV = `TAVAV_27,
TAVQV = `TAVQV_27,
TELQV = `TELQV_27,
TPHQV = `TPHQV_27,
TGLQV = `TGLQV_27,
TELQX = `TELQX_27,
TEHQZ = `TEHQZ_27,
TGLQX = `TGLQX_27,
TGHQZ = `TGHQZ_27,
TOH = `TOH_27 ,
TPHWL = `TPHWL_27,
TWLWH = `TWLWH_27,
TDVWH = `TDVWH_27,
TAVWH = `TAVWH_27,
TWHDX = `TWHDX_27,
TWHAX = `TWHAX_27,
TWHWL = `TWHWL_27,
TVPWH = `TVPWH_27,
TimerPeriod = `TimerPeriod_;
//************************************************************************
initial begin
Other = `FALSE ;
AlgDone = `FALSE ;
Reset = 1'hx ;
Reset <= `TRUE ;
StartUpFlag = `TRUE ;
StartUpFlag <= #2 `FALSE ;
DriveOutputs = `FALSE ;
ToOut = 0 ;
VppError = `FALSE ;
VppErrFlag = `FALSE ;
ClearVppFlag = `FALSE ;
VppFlag = `FALSE ;
WriteSuspended = `FALSE ;
EraseSuspended = `FALSE ;
Suspend = `FALSE ;
ToBeSuspended = `Program;
EraseError = `FALSE ;
TimerClk = 1'b0 ;
ArrayOut = `MaxOutputs'hxxxx ;
CSROut = 0 ;
IDOut = 0 ;
CmdValid = `FALSE ;
WriteToPtr = `NewCmd ;
last_addr_time = 0 ;
curr_addr_time = 0 ;
last_ce_time = 0 ;
curr_ce_time = 0 ;
last_oe_time = 0 ;
curr_oe_time = 0 ;
last_rp_time = 0 ;
curr_rp_time = 0 ;
last_ReadMode_time = 0 ;
curr_ReadMode_time = 0 ;
last_dq_time = 0 ;
curr_dq_time = 0 ;
last_rpb_time = 0 ;
curr_rpb_time = 0 ;
WriteRecovery = 0 ;
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