mmccore.h

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/*
 * Header for MultiMediaCard (MMC)
 *
 * Copyright (c) 2004 ASIC of SOUTHEAST UNIVERSITY
 *
 * Many thanks to PESIA!
 *
 * Based strongly on code by:
 *
 * Author: Yong-iL Joh <[e-mail]>
 *
 * Date  : $Date: 2004/12/22 10:02:10 $ 
 *
 * Versation : 1.0 $
 *          
 */
 
 
#ifndef MMC_MMC_CORE_H
#define MMC_MMC_CORE_H

#include"mmcmedia.h"

#define BASE_MMCC_INIT    0X28000000
#define BASE_MMCC         0X10009000
#define MMCC_STR_STP_CLK  (BASE_MMCC)
#define MMCC_STATUS       (BASE_MMCC+0X4 )
#define MMCC_CLK_RATE     (BASE_MMCC+0X8 )
#define MMCC_CMD_DAT_CONT (BASE_MMCC+0XC )
#define MMCC_RES_TO       (BASE_MMCC+0X10)
#define MMCC_READ_TO      (BASE_MMCC+0X14)
#define MMCC_BLK_LEN      (BASE_MMCC+0X18)
#define MMCC_NOB          (BASE_MMCC+0X1C)
#define MMCC_DAT_COUNT    (BASE_MMCC+0X20)
#define MMCC_INT_MASK     (BASE_MMCC+0X24)
#define MMCC_CMD          (BASE_MMCC+0X28)
#define MMCC_ARG          (BASE_MMCC+0X2C)
#define MMCC_RESPONSE0    (BASE_MMCC+0X30)
#define MMCC_RESPONSE1    (BASE_MMCC+0X34)
#define MMCC_RESPONSE2    (BASE_MMCC+0X38)
#define MMCC_RESPONSE3    (BASE_MMCC+0X3C)
#define MMCC_WRITE_BUFER_ACCESS (BASE_MMCC+0X40)
#define MMCC_READ_BUFER_ACCESS (BASE_MMCC+0X44)

//new gpt 
#define		GPT_BASE		0x10003000
#define		GPT1_COMP		(GPT_BASE + 0x00)
#define		GPT1_CNT		(GPT_BASE + 0x04)
#define		GPT1_CNTL		(GPT_BASE + 0x08)
#define		GPT1_EOI		(GPT_BASE + 0x0c)
#define		GPT1_IST		(GPT_BASE + 0x10)

#define		GPT2_COMP		(GPT_BASE + 0x14)
#define		GPT2_CNT		(GPT_BASE + 0x18)
#define		GPT2_CNTL		(GPT_BASE + 0x1C)
#define		GPT2_EOI		(GPT_BASE + 0x20)
#define		GPT2_IST		(GPT_BASE + 0x24)

#define		GPT3_COMP		(GPT_BASE + 0x28)
#define		GPT3_CNT		(GPT_BASE + 0x2C)
#define		GPT3_CNTL		(GPT_BASE + 0x30)
#define		GPT3_EOI		(GPT_BASE + 0x34)
#define		GPT3_IST		(GPT_BASE + 0x38)

#define		GPT4_COMP		(GPT_BASE + 0x3C)
#define		GPT4_CNT		(GPT_BASE + 0x40)
#define		GPT4_CNTL		(GPT_BASE + 0x44)
#define		GPT4_EOI		(GPT_BASE + 0x48)
#define		GPT4_IST		(GPT_BASE + 0x4C)

#define		GPT_GLB_EOI		(GPT_BASE + 0XA0)
#define		GPT_GLB_IST		(GPT_BASE + 0XA4)
#define		GPT_GLB_RIST	(GPT_BASE + 0XA8)

#define		GPT_EN		0X01
#define		GPT_NOM		0X02
#define		GPT_FRU		0X00
#define		GPT_IDIS	0X04
#define		GPT_IEN		0X00

/*this is register for DMA*/
#define 	DMACbase			0x11000000
#define 	DMACIntStatus			(DMACbase+0x1020) 			//Read
#define 	DMACIntTCStatus			(DMACbase+0x1050) 			//Read
#define 	DMACIntTCClear			(DMACbase+0x1060) 			//Write
#define 	DMACRawIntTCStatus		(DMACbase+0x1070) 			//Read
#define 	DMACIntErrorStatus		(DMACbase+0x1080) 			//Read
#define 	DMACIntErrClr			(DMACbase+0x1090) 			//Write
#define 	DMACRawIntErrorStatus   	(DMACbase+0x10a0) 			//Read
#define 	DMACEnbldChns			(DMACbase+0x10B0) 			//Read;  Indicate which channel can be used;
#define   ADDRESS_CONFIGURATION   	(DMACbase+0x10C0)
   
#define 	DMACC0SrcAddr			(DMACbase+0x1000)			//DMA channel 0 registers;
#define 	DMACC0DestAddr			(DMACbase+0x1004)
#define 	DMACC0Control			(DMACbase+0x100c)
#define 	DMACC0Configuration		(DMACbase+0x1010)
#define 	DMACC1SrcAddr			(DMACbase+0x1100)			//DMA channel 1 registers;   R/W
#define 	DMACC1DestAddr			(DMACbase+0x1104)
#define 	DMACC1Control			(DMACbase+0x110c)
#define 	DMACC1Configuration		(DMACbase+0x1110)
#define 	DMACC2SrcAddr			(DMACbase+0x1200)			//DMA channel 2 registers;   R/W
#define 	DMACC2DestAddr			(DMACbase+0x1204)
#define 	DMACC2Control			(DMACbase+0x120c)
#define 	DMACC2Configuration		(DMACbase+0x1210)
#define 	DMACC3SrcAddr			(DMACbase+0x1300)			//DMA channel 3 registers;   R/W
#define 	DMACC3DestAddr			(DMACbase+0x1304)
#define 	DMACC3Control			(DMACbase+0x130c)
#define 	DMACC3Configuration		(DMACbase+0x1310)
#define 	DMACC4SrcAddr			(DMACbase+0x1400)			//DMA channel 4 registers;   R/W
#define 	DMACC4DestAddr			(DMACbase+0x1404)
#define 	DMACC4Control			(DMACbase+0x140c)
#define 	DMACC4Configuration		(DMACbase+0x1410)
#define 	DMACC5SrcAddr			(DMACbase+0x1500)			//DMA channel 5 registers;   R/W
#define 	DMACC5DestAddr			(DMACbase+0x1504)
#define 	DMACC5Control			(DMACbase+0x150c)
#define 	DMACC5Configuration		(DMACbase+0x1510) 

//added by jzp
//typedef unsigned char   	u8;     /* unsigned 8-bit integer */
//typedef unsigned short  	u16;     /* unsigned 16-bit integer */
//typedef unsigned long   	U32;     /* unsigned 32-bit integer */
typedef	volatile U32 *		RP;
typedef	volatile U16 *		RP16;
typedef	volatile U8  *		RP8;

struct request
{
   // U32*     pNxtRequest;
   // U32*     pPrvRequest;
    U32      cmd;       
    U32      sector; 
    U32      block_len;
    U32      nr_sectors; 	
    U8*     buffer;
} ;

struct mmc_request {                              
	int               index;      /* Slot index - used for CS lines */                                          	
	U32               cmd;        /* Command to send */
	U32               arg;        /* Argument to send */
                                                 
	/* Data transfer (these may be modified at the low level) */	
	U32               nob; 
	U32               block_len;  	
    U8              *buffer;    
	/* Results */
	U8                response[18]; /* Buffer to store response - CRC is optional */
	//enum mmc_result_t result;
};

struct mmc_io_request {
	int            id;         /* Card index     */
	U32            cmd;        /* READ or WRITE  */
	U32            sector;     /* Start address  */
	U32            nr_sectors; /* Length of read */
	U32            block_len;  /* Size of sector (sanity check) */
	U8 *buffer;     /* Data buffer    */
};
struct mmc_dev {
	struct mmc_request        request;               // Active request to the low-level driver
	struct mmc_io_request    *io_request;            // Active transfer request from the high-level media io
	int    num_slots;                 // Copied from the slot driver; used when slot driver shuts down
	/* State maintenance */
	int    state;  
	int    suspended;
};

#endif