📄 arm1176-dormantmode-example_c.s
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; Save remaining CP15 Non-secure registers ; Also save common Aux ctrl and Coprocessor access ctrl registers MRC p15,0,r2,c5,c0,0 ; NS DFSR MRC p15,0,r3,c5,c0,1 ; NS IFSR MRC p15,0,r4,c6,c0,0 ; NS FAR MRC p15,0,r5,c6,c0,2 ; NS IFAR MRC p15,0,r6,c7,c4,0 ; NS PA MRC p15,0,r7,c9,c2,0 ; NS TCM Selection MRC p15,0,r8,c13,c0,2 ; NS User R/W Thread/PID MRC p15,0,r9,c13,c0,3 ; NS User RO Thread/PID MRC p15,0,r10,c13,c0,4 ; NS Priv Only Thread/PID MRC p15,0,r11,c12,c0,0 ; NS Vector Base Address MRC p15,0,r12,c1,c0,1 ; Auxiliary Control STMIA r1!,{r2-r12} ; Save ; Clear the NS bit (to make interrupt handler easier). ; (If you disabled interrupts while the NS bit was set, ; you can re-enable them now.) MRC p15,0,r0,c1,c1,0 ; Read S Config BIC r0,r0,#1 ; Clear NS bit MCR p15,0,r0,c1,c1,0 ; Write S Config ; If we have a DMA, save DMA state (both channels) and ; stop running and queued DMA channels. ; If either channel has stopped with an error, we cannot ; restore this error status. This code will abandon entry to ; dormant mode and return. Alternatively you can change this code ; to process the DMA error(s) and continue. ; This code checks if the DMA is present by reading the DMA ID ; & Status reg. If your code runs on a system that never has ; an internal DMA engine you can remove this code section. MRC p15,0,r0,c11,c0,0 ; Read DMA ID & Status CMP r0,#3 ; Do we have a DMA? BNE no_DMA ; No - skip DMA save MRC p15,0,r2,c11,c1,0 ; User Accessibility Reg MRC p15,0,r3,c11,c2,0 ; Channel Number MOV r0,#0 MCR p15,0,r0,c11,c2,0 ; Select Channel 0 MRC p15,0,r4,c11,c8,0 ; DMA channel status CMP r4,#3 ; Is there an error? BHI quit_dormant_entry ; Yes: quit MCR p15,0,r0,c11,c3,0 ; No: stop the channel MOV r0,#1 MCR p15,0,r0,c11,c2,0 ; Select Channel 1 MRC p15,0,r10,c11,c8,0 ; DMA channel status CMP r10,#3 ; Is there an error? BHI quit_dormant_entry ; Yes: quit MCR p15,0,r0,c11,c3,0 ; No: stop the channel MOV r0,#0 MCR p15,0,r0,c11,c2,0 ; Select Channel 0wait_DMA0idle MRC p15,0,r0,c11,c8,0 ; DMA channel status ANDS r0,r0,#3 ; Is the channel idle CMPNE r0,#3 ; or Complete/Error? BNE wait_DMA0idle ; Poll until it is MRC p15,0,r5,c11,c4,0 ; Control Register MRC p15,0,r6,c11,c5,0 ; Internal Start Address MRC p15,0,r7,c11,c6,0 ; External Start Address MRC p15,0,r8,c11,c7,0 ; Internal End Address MRC p15,0,r9,c11,c15,0 ; Context ID STMIA r1!,{r2-r9} ; Save MCR p15,0,r0,c11,c3,2 ; Clear channel 0 MOV r0,#1 MCR p15,0,r0,c11,c2,0 ; Select Channel 1 MOV r4,r10 ; Prior channel statuswait_DMA1idle MRC p15,0,r0,c11,c8,0 ; DMA channel status ANDS r0,r0,#3 ; Is the channel idle CMPNE r0,#3 ; or Complete/Error? BNE wait_DMA1idle ; Poll until it is MRC p15,0,r5,c11,c4,0 ; Control Register MRC p15,0,r6,c11,c5,0 ; Internal Start Address MRC p15,0,r7,c11,c6,0 ; External Start Address MRC p15,0,r8,c11,c7,0 ; Internal End Address MRC p15,0,r9,c11,c15,0 ; Context ID STMIA r1!,{r4-r9} ; Save MCR p15,0,r0,c11,c3,2 ; Clear channel 1no_DMA ; NB - Jazelle-DBX registers (CP14) were not forgotten. They ; should not be saved or restored by this routine. The ; Virtual Machine should be relied upon to re-initialize ; Jazelle-DBX state. ; Save TLB Lockdown Index MRC p15,5,r5,c15,c4,2 ; TLB Lockdown Index STMIA r1!,{r5} ; Save ; Save lockdown region of TLB MOV r0,#0 MCR p15,5,r0,c15,c4,2 ; Select lockdown entry 0 MRC p15,5,r2,c15,c5,2 ; Read Main TLB VA MRC p15,5,r3,c15,c6,2 ; Read Main TLB PA MRC p15,5,r4,c15,c7,2 ; Read Main TLB Attr MOV r0,#1 MCR p15,5,r0,c15,c4,2 ; Select lockdown entry 1 MRC p15,5,r5,c15,c5,2 ; Read Main TLB VA MRC p15,5,r6,c15,c6,2 ; Read Main TLB PA MRC p15,5,r7,c15,c7,2 ; Read Main TLB Attr MOV r0,#2 MCR p15,5,r0,c15,c4,2 ; Select lockdown entry 2 MRC p15,5,r8,c15,c5,2 ; Read Main TLB VA MRC p15,5,r9,c15,c6,2 ; Read Main TLB PA MRC p15,5,r10,c15,c7,2 ; Read Main TLB Attr MOV r0,#3 MCR p15,5,r0,c15,c4,2 ; Select lockdown entry 3 MRC p15,5,r11,c15,c5,2 ; Read Main TLB VA MRC p15,5,r12,c15,c6,2 ; Read Main TLB PA MRC p15,5,r13,c15,c7,2 ; Read Main TLB Attr STMIA r1!,{r2-r13} ; Save MOV r0,#4 MCR p15,5,r0,c15,c4,2 ; Select lockdown entry 4 MRC p15,5,r2,c15,c5,2 ; Read Main TLB VA MRC p15,5,r3,c15,c6,2 ; Read Main TLB PA MRC p15,5,r4,c15,c7,2 ; Read Main TLB Attr MOV r0,#5 MCR p15,5,r0,c15,c4,2 ; Select lockdown entry 5 MRC p15,5,r5,c15,c5,2 ; Read Main TLB VA MRC p15,5,r6,c15,c6,2 ; Read Main TLB PA MRC p15,5,r7,c15,c7,2 ; Read Main TLB Attr MOV r0,#6 MCR p15,5,r0,c15,c4,2 ; Select lockdown entry 6 MRC p15,5,r8,c15,c5,2 ; Read Main TLB VA MRC p15,5,r9,c15,c6,2 ; Read Main TLB PA MRC p15,5,r10,c15,c7,2 ; Read Main TLB Attr MOV r0,#7 MCR p15,5,r0,c15,c4,2 ; Select lockdown entry 7 MRC p15,5,r11,c15,c5,2 ; Read Main TLB VA MRC p15,5,r12,c15,c6,2 ; Read Main TLB PA MRC p15,5,r13,c15,c7,2 ; Read Main TLB Attr STMIA r1!,{r2-r13} ; Save ; Save the state of any memory-mapped peripherals that are ; powered down in dormant mode. ; For example: the validation trickbox registers and ; Peripheral Protection Unit (PPU). ; Replace this code with your own code to save the state of ; your memory-mapped peripherals.TB_BASE EQU 0x13000000 ; Trickbox base address LDR r0,=TB_BASE LDR r2,[r0,#0x64] ; Trickbox abort addr LDR r3,[r0,#0x44] ; Trickbox abort range 1 LDR r4,[r0,#0x40] ; Trickbox abort range 2 ADD r0,r0,#0x230 ; PPU base address LDMIA r0,{r5-r12} ; PPU registers STMIA r1!,{r2-r12} ; Save ; Enable access to all coprocessors to save coproc & VFP state ; You can omit this if you have no coprocessors and no VFP LDR r0,=0xFFFFFFFF ; Enable all coprocs MCR p15,0,r0,c1,c0,2 ; Write coproc acc ctrl ; If we have a VFP coprocessor, save the VFP system regs and ; register bank. ; This code checks if the VFP is present by reading the ; coprocessor access control reg bits 23-20. If your code runs ; on a system that never has a VFP, you can remove this code. ; If your system always has a VFP, you can remove the check. MRC p15,0,r0,c1,c0,2 ; Coproc access ctrl ANDS r0,r0,#0xF << 20 ; VFP present? BEQ no_VFP ; No - skip VFP save FMRX r2,FPEXC ; VFP Exception ORR r0,r2,#1 << 30 ; Enable VFP FMXR FPEXC,r0 ; Write VFP Exception FMRX r3,FPSCR ; VFP Status & Control FMRX r4,FPINST ; VFP Instruction FMRX r5,FPINST2 ; VFP Instruction 2 STMIA r1!,{r2-r5} ; Save FSTMIAX r1!,{d0-d15} ; Save VFP register bankno_VFP ; Save the registers of all other coprocessors. ; As all coprocessors are different, we cannot write generic ; code here to save the registers of any coprocessor. If you ; have coprocessors other than the VFP, write your own code to ; save all of their registers to memory. Otherwise, remove this ; section of code. ; The example code here saves the validation generic ; coprocessors p4 & p5. ; Note: you can test for the presence of coprocessors by reading ; the appropriate bits of the coprocessor access control reg, ; but you still need to know what state must be saved for each ; individual coprocessor present in the system. STC p4,c0,[r1],#4 ; Save coproc p4 regs STC p4,c1,[r1],#4 STC p4,c2,[r1],#4 STC p4,c3,[r1],#4 STC p4,c4,[r1],#4 STC p4,c5,[r1],#4 STC p4,c6,[r1],#4 STC p4,c7,[r1],#4 STC p4,c8,[r1],#4 STC p4,c9,[r1],#4 STC p4,c10,[r1],#4 STC p4,c11,[r1],#4 STC p4,c12,[r1],#4 STC p4,c13,[r1],#4 STC p4,c14,[r1],#4 STC p4,c15,[r1],#4 STC p5,c0,[r1],#4 ; Save coproc p5 regs STC p5,c1,[r1],#4 STC p5,c2,[r1],#4 STC p5,c3,[r1],#4 STC p5,c4,[r1],#4 STC p5,c5,[r1],#4 STC p5,c6,[r1],#4 STC p5,c7,[r1],#4 STC p5,c8,[r1],#4 STC p5,c9,[r1],#4 STC p5,c10,[r1],#4 STC p5,c11,[r1],#4 STC p5,c12,[r1],#4⌨️ 快捷键说明
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