arm1176-dormantmode-example_c.s

The application described in this document is for a product that is subject to continuous developmen

;*******************************************************************************
;*
;* The confidential and proprietary information contained in this file may
;* only be used by a person authorised under and to the extent permitted
;* by a subsisting licensing agreement from ARM Limited.
;*
;*              (C) COPYRIGHT 2004 ARM Limited.
;*                      ALL RIGHTS RESERVED
;*
;* This entire notice must be reproduced on all copies of this file
;* and copies of this file may only be made by a person if such person is
;* permitted to do so under the terms of a subsisting license agreement
;* from ARM Limited.
;*
;*              Config to simulate the dormant mode
;*              ===================================
;*
;*      Origin: CPU Validation
;*   $Revision: 1.8 $
;*      $Date: Wed Oct 31 17:46:55 2007 $
;*
;*******************************************************************************

                AREA    dormantMode, CODE


;*******************************************************************************
;*      Configuration and constants
;*******************************************************************************

; Change the following definition to the address at the start of your dormant
; mode state saving address space.  This memory region should be defined as
; write back for best performance.  This address should be flat mapped, so that
; the physical and virtual addresses are the same.  To ensure security of saved
; state, this memory region should be defined as Secure.
DORMANTSTORE    EQU     dormantstore_area

; Specify whether Dormant mode entry/exit code uses its own static memory setup
; i.e. after saving memory setup state it changes to a memory setup which can
; be statically restored from constants after reset, in which case the original
; memory setup state can be saved into cache
                GBLL    DM_STATICMEM
DM_STATICMEM    SETL    {FALSE}                         ; {TRUE} or {FALSE}

; Aliases for mode encodings - do not change
MODE_USR        EQU     0x10
MODE_FIQ        EQU     0x11
MODE_IRQ        EQU     0x12
MODE_SVC        EQU     0x13
MODE_ABT        EQU     0x17
MODE_UND        EQU     0x1B
MODE_MON        EQU     0x16
MODE_SYS        EQU     0x1F


;*******************************************************************************
;*      Dormant mode entry
;*******************************************************************************

  ; This code assumes that the operating system will make the decision to
  ; enter dormant mode.  The operating system must call this dormant mode
  ; entry code in Secure Monitor mode using an instruction of the form:
  ;     BL dormant_entry
  ; as the dormant mode exit code returns using a MOV pc,r14 instruction.  The
  ; entry code assumes that it is in Secure Monitor mode and does not check for
  ; this.

  ; Running in Secure Monitor mode allows easy access to both Secure and
  ; Non-secure state, and permits saving all state to a Secure memory region.
  ; The means of entering Secure Monitor mode is left to the operating system,
  ; but would typically be a SMI call to request entry to dormant mode, and the
  ; Secure Monitor code would then branch to this code using a BL instruction.

  ; The dormant mode entry code saves all required state in the correct order.
  ; You must make some modifications to this code as explained by the comments
  ; within it.  The most important change is to add your system-dependent method
  ; of setting up your system's power controller so that it will enter dormant
  ; mode when it sees the macrocell output STANDBYWFI go high.  Full details
  ; are given in the comments.

  ; Information about the dormant mode exit code is given at the start of that
  ; code.

                EXPORT  dormant_entry

dormant_entry
                ; Assume we are in Secure Monitor mode.
                ; Save general purpose registers, Monitor mode registers and SPSR
                STR     r0,r0_store                     ; Temporary store
                LDR     r0,=DORMANTSTORE                ; Get state save addr
                STR     r1,[r0,#4]                      ; Save r1
                MOV     r1,r0                           ; Get state save addr
                LDR     r0,r0_store                     ; Restore r0
                STR     r0,[r1],#8                      ; Save r0
                STMIA   r1!,{r2-r14}                    ; Save r2-r14 (gen/Mon)
                MRS     r0,SPSR                         ; Get SPSR (Mon)
                STR     r0,[r1],#4                      ; Save SPSR

                ; Save the Secure Configuration register, then clear the NS bit
                ; to remain in the Secure world and select Secure versions of
                ; banked registers
                MRC     p15,0,r0,c1,c1,0                ; Read S Config
                STR     r0,[r1],#4                      ; Save
                BIC     r0,r0,#1                        ; Clear NS bit
                MCR     p15,0,r0,c1,c1,0                ; Write S Config

                ; Save the CPSR
                MRS     r0,CPSR                         ; Get CPSR
                STR     r0,[r1],#4                      ; Save CPSR
                
                ; Disable interrupts until mode regs & SPSRs are saved
                ; Also change to System mode for next section
                CPSID   if,#MODE_SYS

                ; Save System/User mode registers
                STMIA   r1!,{r13-r14}                   ; Save r13-r14 (Sys/User)

                ; Save FIQ mode registers and SPSR
                CPS     #MODE_FIQ
                STMIA   r1!,{r8-r14}                    ; Save r8-r14 (FIQ)
                MRS     r0,SPSR                         ; Get SPSR
                STR     r0,[r1],#4                      ; Save SPSR

                ; Save IRQ mode registers and SPSR
                CPS     #MODE_IRQ
                STMIA   r1!,{r13-r14}                   ; Save r13-r14 (IRQ)
                MRS     r0,SPSR                         ; Get SPSR
                STR     r0,[r1],#4                      ; Save SPSR

                ; Save Abort mode registers and SPSR
                CPS     #MODE_ABT
                STMIA   r1!,{r13-r14}                   ; Save r13-r14 (Abort)
                MRS     r0,SPSR                         ; Get SPSR
                STR     r0,[r1],#4                      ; Save SPSR

                ; Save Supervisor mode registers and SPSR
                CPS     #MODE_SVC
                STMIA   r1!,{r13-r14}                   ; Save r13-r14 (SVC)
                MRS     r0,SPSR                         ; Get SPSR
                STR     r0,[r1],#4                      ; Save SPSR

                ; Save Undefined mode registers and SPSR
                CPS     #MODE_UND
                STMIA   r1!,{r13-r14}                   ; Save r13-r14 (Undef)
                MRS     r0,SPSR                         ; Get SPSR
                STR     r0,[r1],#4                      ; Save SPSR

                ; Return to Secure Monitor mode and enable interrupts
                CPSIE   aif,#MODE_MON

                ; Save TLB lockdown register, then force page table walks to
                ; write into the associative region of the TLB, to avoid
                ; changing the lockdown region
                MRC     p15,0,r2,c10,c0,0               ; TLB Lockdown
                STR     r2,[r1],#4                      ; Save
                BIC     r2,r2,#1                        ; Clear P bit
                MCR     p15,0,r2,c10,c0,0               ; Write TLB Lockdown

  ; If Dormant mode has its own static memory setup, save Secure memory system
  ; control registers then change to the static memory setup.
  ; This is only worth doing if both the original memory setup and the static
  ; setup enable write-back into the data cache.
  [ DM_STATICMEM
                MRC     p15,0,r2,c1,c0,0                ; S Control
                MRC     p15,0,r3,c2,c0,0                ; S TTBR0
                MRC     p15,0,r4,c2,c0,1                ; S TTBR1
                MRC     p15,0,r5,c2,c0,2                ; S TTBCR
                MRC     p15,0,r6,c3,c0,0                ; S DAC
                MRC     p15,0,r7,c13,c0,0               ; S FCSE PID
                MRC     p15,0,r8,c13,c0,1               ; S Context ID
                MRC     p15,0,r9,c10,c2,0               ; S Primary Region Remap
                MRC     p15,0,r10,c10,c2,1              ; S Normal Memory Remap
                MRC     p15,0,r11,c15,c2,4              ; S PP Memory Remap
                MRC     p15,0,r12,c9,c0,0               ; D Cache Lockdown
                MRC     p15,0,r13,c9,c0,1               ; I Cache Lockdown
                MRC     p15,0,r14,c9,c8,0               ; Cache Behavior Override
                STMIA   r1!,{r2-r14}                    ; Save
  ; Now set up the static memory configuration for Dormant mode.
  ; This may involve changing Secure TTBR regs to use new page tables, or
  ; disabling the MMU and remapping memory to write-back. If you disable the MMU
  ; here, write 0x00000000 to the Secure FCSE PID register first. You may also
  ; need to change your Level 2 memory Secure/Non-secure memory mapping.
  ]
  ; Note: if you do not have a separate static memory setup for dormant mode,
  ; the above state will be saved later after disabling the caches & MMU.

                ; Save remaining CP15 Secure registers
                MRC     p15,0,r2,c1,c1,1                ; S Debug Enable
                MRC     p15,0,r3,c1,c1,2                ; NS access control
                MRC     p15,0,r4,c5,c0,0                ; S DFSR
                MRC     p15,0,r5,c5,c0,1                ; S IFSR
                MRC     p15,0,r6,c6,c0,0                ; S FAR
                MRC     p15,0,r7,c6,c0,2                ; S IFAR
                MRC     p15,0,r8,c7,c4,0                ; S PA
                MRC     p15,0,r9,c9,c2,0                ; S TCM Selection
                MRC     p15,0,r10,c13,c0,2              ; S User R/W Thread/PID
                MRC     p15,0,r11,c13,c0,3              ; S User RO Thread/PID
                MRC     p15,0,r12,c13,c0,4              ; S Priv Only Thread/PID
                MRC     p15,0,r13,c1,c0,2               ; Coproc Access Control - read in secure state only
                STMIA   r1!,{r2-r13}                    ; Save

  ; Set the NS bit to select NS versions of banked registers
  ; Note: if an interrupt occurs during this code's execution (in Monitor mode
  ; with the NS bit set), the NS bit will be automatically cleared to ensure
  ; that the processor remains in the Secure world. Your interrupt handler must
  ; recognise this, and if it decides to continue entry to Dormant mode, it must
  ; re-enter Monitor mode and set the NS bit before returning to this code.
  ; Alternatively, disable interrupts during this section of code.
                MRC     p15,0,r0,c1,c1,0                ; Read S Config
                ORR     r0,r0,#1                        ; Set NS bit
                MCR     p15,0,r0,c1,c1,0                ; Write S Config

                ; Save Non-secure memory system control registers
                MRC     p15,0,r2,c7,c10,6               ; NS Cache Dirty Status
                MRC     p15,0,r3,c1,c0,0                ; NS Control
                MRC     p15,0,r4,c2,c0,0                ; NS TTBR0
                MRC     p15,0,r5,c2,c0,1                ; NS TTBR1
                MRC     p15,0,r6,c2,c0,2                ; NS TTBCR
                MRC     p15,0,r7,c3,c0,0                ; NS DAC
                MRC     p15,0,r8,c13,c0,0               ; NS FCSE PID
                MRC     p15,0,r9,c13,c0,1               ; NS Context ID
                MRC     p15,0,r10,c10,c2,0              ; NS Primary Region Remap
                MRC     p15,0,r11,c10,c2,1              ; NS Normal Memory Remap
                MRC     p15,0,r12,c15,c2,4              ; NS PP Memory Remap
                STMIA   r1!,{r2-r12}                    ; Save