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📄 arm1136-shutdownmode-example_c.s

📁 The application described in this document is for a product that is subject to continuous developmen
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                MRC     p15,0,r4,c15,c12,2              ; Count register 0
                MRC     p15,0,r5,c15,c12,3              ; Count register 1
                STMIA   r1!,{r2-r5}                     ; Save

                ; Save the Debug registers
                MRC     p14,0,r2,c0,c1,0                ; DSCR
                ORR     r0,r2,#1 << 15                  ; Select & enable Debug
                BIC     r0,r0,#1 << 14                  ;  monitor mode
                MCR     p14,0,r0,c0,c1,0                ; Write DSCR
                MRC     p14,0,r3,c0,c0,4                ; BVR0
                MRC     p14,0,r4,c0,c1,4                ; BVR1
                MRC     p14,0,r5,c0,c2,4                ; BVR2
                MRC     p14,0,r6,c0,c3,4                ; BVR3
                MRC     p14,0,r7,c0,c4,4                ; BVR4
                MRC     p14,0,r8,c0,c5,4                ; BVR5
                MRC     p14,0,r9,c0,c0,5                ; BCR0
                MRC     p14,0,r10,c0,c1,5               ; BCR1
                MRC     p14,0,r11,c0,c2,5               ; BCR2
                MRC     p14,0,r12,c0,c3,5               ; BCR3
                MRC     p14,0,r13,c0,c4,5               ; BCR4
                MRC     p14,0,r14,c0,c5,5               ; BCR5
                STMIA   r1!,{r2-r14}                    ; Save
                MRC     p14,0,r2,c0,c0,6                ; WVR0
                MRC     p14,0,r3,c0,c1,6                ; WVR1
                MRC     p14,0,r4,c0,c0,7                ; WCR0
                MRC     p14,0,r5,c0,c1,7                ; WCR1
                MRC     p14,0,r6,c0,c7,0                ; VTR
                STMIA   r1!,{r2-r6}                     ; Save

                ; Save memory system control registers
                MRC     p15,0,r2,c1,c0,0                ; Control
                MRC     p15,0,r3,c2,c0,0                ; TTBR0
                MRC     p15,0,r4,c2,c0,1                ; TTBR1
                MRC     p15,0,r5,c2,c0,2                ; TTBCR
                MRC     p15,0,r6,c3,c0,0                ; DAC
                MRC     p15,0,r7,c13,c0,0               ; FCSE PID
                MRC     p15,0,r8,c13,c0,1               ; Context ID
                STMIA   r1!,{r2-r8}                     ; Save
                MRC     p15,0,r2,c15,c2,0               ; Data Mem Remap
                MRC     p15,0,r3,c15,c2,1               ; Instr Mem Remap
                MRC     p15,0,r4,c15,c2,2               ; DMA Mem Remap
                MRC     p15,0,r5,c15,c2,4               ; PP Mem Remap
                MRC     p15,7,r6,c15,c0,0               ; Cache Debug Control
                MRC     p15,7,r7,c15,c1,0               ; TLB Debug Control
                MRC     p15,0,r8,c9,c1,0                ; D TCM Region
                MRC     p15,0,r9,c9,c1,1                ; I TCM Region
                STMIA   r1!,{r2-r9}                     ; Save
                ; ARM1136 rev1 has two extra memory system registers
                MRC     p15,0,r0,c0,c0,0                ; Read ID code
                ANDS    r0,r0,#0xF << 20                ; Is this a rev0 device?
                BEQ     rev0_skip2                      ; Yes: skip
                MRC     p15,0,r2,c10,c2,0               ; Primary Region Remap
                MRC     p15,0,r3,c10,c2,1               ; Normal Memory Remap
                STMIA   r1!,{r2-r3}                     ; Save
rev0_skip2

                ; Note: we do not save Cache Lockdown registers, as we lose the
                ; data or instructions in the locked ways.  For workarounds
                ; see the equivalent point in the shutdown mode restore code,
                ; and the shutdown mode documentation.

                ; Save the address at the end of the state saving.
                ; Save this at a known fixed address so we can restore from it.
                STR     r1,shutdown_end

                ; Wait for any running DMA operations (to save the contents of
                ; TCMs) to complete
                MRC     p15,0,r0,c11,c0,0               ; DMA Status - present
                CMP     r0,#3                           ; DMA present?
                BNE     no_waitTCMsave                  ; No: skip wait
wait_TCMsave    MRC     p15,0,r2,c11,c0,1               ; DMA Status - queued
                MRC     p15,0,r3,c11,c0,2               ; DMA Status - running
                CMP     r2,#0                           ; Any channel queued?
                BNE     wait_TCMsave                    ; Yes: wait
                CMP     r3,#0                           ; Any channel running?
                BNE     wait_TCMsave                    ; Yes: wait
                ; Clear both DMA channels (assume no errors occurred)
                MOV     r2,#0
		MCR	p15,0,r2,c11,c2,0		; Select channel 0
		MCR	p15,0,r2,c11,c3,2		; Clear channel 0
		MOV	r3,#1
		MCR	p15,0,r3,c11,c2,0		; Select channel 1
		MCR	p15,0,r2,c11,c3,2		; Clear channel 1
no_waitTCMsave

                ; Disable interrupts, MMU and data cache to make it easier
                ; to clean the data cache and data SmartCache (if required)
                CPSID   if                              ; Disable interrupts
                MRC     p15,0,r0,c1,c0,0                ; Read ctrl reg
                BIC     r10,r0,#2_101                   ; Disable Dcache & MMU
                MCR     p15,0,r10,c1,c0,0               ; Write ctrl reg

                ; Clean the entire data cache
                MCR     p15,0,r0,c7,c10,0

                ; If the data TCM is enabled as SmartCache, clean all of it.
                ; This is done using clean range by VA.  As we have disabled
                ; the MMU, we have a flat VA to PA mapping, so we can take the
                ; physical base address of the D TCM as the start VA, and add
                ; the size of the TCM to it to get the end VA.
                ; If you never enable TCMs as SmartCache, or you have no TCMs,
                ; you can remove this code.  If the base address and/or size
                ; of your D TCM enabled as SmartCache is constant, you can
                ; replace some of this code with the constant values.
                AND     r0,r8,#3
                CMP     r0,#3                           ; D TCM enabled as SC?
                BNE     no_SCclean                      ; No: skip SC clean
                BIC     r0,r8,#0xFF                     ; Get base address
                ANDS    r1,r8,#0x7C                     ; Get TCM size: is it 0?
                BEQ     no_SCclean                      ; Yes: skip SC clean
                MOV     r1,r1,LSR #2                    ; Move TCM size to LSBs
                MOV     r2,#0xF << 5                    ; Addr bits [15:12] mask
                BIC     r0,r0,r2,LSL r1                 ; Mask invalid addr bits
                MOV     r3,#1 << 9
                MOV     r3,r3,LSL r1                    ; Get TCM size in bytes
                ADD     r4,r0,r3                        ; Base addr + TCM size
                SUB     r4,r4,#4                        ; Last word in TCM addr
                MCRR    p15,0,r4,r0,c12                 ; Clean D SmartCache
no_SCclean

                ; Set up your power controller so that it will enter shutdown
                ; mode when it next sees STANDBYWFI macrocell output go high.
                ; When this occurs, the power controller must drive the
                ; ARM1136's reset inputs low and hold them low while it removes
                ; the power supply to the logic, but not the RAMs.
                ; When the power controller wishes to exit shutdown mode, it
                ; must drive the ARM1136's reset inputs low and hold them low
                ; while it restores the power supply to the ARM1136.  When it
                ; de-asserts the reset inputs, the reset code must identify that
                ; it is coming out of shutdown mode and branch to the shutdown
                ; mode restore code to restore system state.

                ; The validation world uses a memory-mapped trickbox feature to
                ; model the power controller:
                LDR     r1,=TB_BASE                     ; Set up the shutdown
                LDR     r0,=0x3000                      ;  mode trickbox feature
                STR     r0,[r1,#0xA4]

                ; Drain the write buffer
                MCR     p15,0,r0,c7,c10,4

                ; Wait for interrupt (asserts STANDBYWFI macrocell output)
                MCR     p15,0,r0,c7,c0,4

quit_shutdown_entry
  ; We come here if either DMA channel has stopped with an error.
  ; Restore any registers we have changed and return.
                MCR     p15,0,r3,c11,c2,0               ; Restore DMA channel no
                LDR     r1,=SHUTDOWNSTORE               ; Get state save addr
                LDR     r2,[r1,#0x90]                   ; Load TLB lockdown
                MCR     p15,0,r2,c10,c0,0               ; Restore TLB lockdown
                LDR     r0,[r1,#0x3C]                   ; Load CPSR
                MSR     CPSR_cxsf,r0                    ; Restore CPSR
                LDMIA   r1,{r0-r14}                     ; Restore r0-r14 (SYS)
                MOV     pc,r14                          ; Return

  ; END OF SHUTDOWN MODE ENTRY CODE

; Data pool
shutdown_end    DCD     0
r0_store        DCD     0
                LTORG


;*******************************************************************************
;*      Shutdown mode exit
;*******************************************************************************

  ; This code assumes that the reset exception handler determines (by whatever
  ; means) that the reset is due to exiting shutdown mode, and the reset handler
  ; then branches (by any means) to this shutdown mode exit code.  The reset
  ; handler does not need to configure the ARM1136 in any way before this.  The
  ; shutdown mode exit code assumes that it is entered in a privileged mode.

  ; The shutdown mode exit code restores all required state in the correct order
  ; (generally the opposite order from that in which it was saved).
  ; You must make some modifications to this code as explained by the comments
  ; within it.  When all state is restored, the shutdown mode exit code restores
  ; the original CPSR, thus entering System mode (as shutdown mode entry was
  ; called in System mode), and returns to the instruction after the the
  ; original call to the shutdown mode entry code, using the following
  ; instruction:
  ;     MOV pc,r14
  ; This assumes that the shutdown mode entry code was called in System mode
  ; using an instruction of the form:
  ;     BL shutdown_entry

  ; Information about the shutdown mode entry code is given at the start of that
  ; code.

                EXPORT  shutdown_exit

shutdown_exit
                ; Assume we are in a privileged mode.
                ; Enter system mode and ensure interrupts are disabled
                CPSID   aif,#MODE_SYS

                ; Load the address at the end of the state save memory region
                LDR     r1,shutdown_end

                ; Note: we do not save and restore the Cache Lockdown registers.
                ; Powering down the cache RAMs in shutdown mode loses the
                ; contents of any locked cache ways, so there is no point
                ; locking ways that are now empty.
                ; If you use the cache lockdown features, there are two methods
                ; to restore locked cache ways:
                ; 1) If the locked ways and their contents are static, you can
                ;    simply repeat the code that you used to fill and lock the
                ;    cache ways.
                ; 2) If cache way locking or the addresses that are locked into
                ;    cache ways vary, it is possible to identify the addresses
                ;    of lines locked in a cache way, save these addresses, then
                ;    refill the cache lines and relock them on exiting shutdown
                ;    mode.  The procedure is described in the shutdown mode
                ;    documentation.

                ; Restore memory system control registers
                ; ARM1136 rev1 has two extra memory system registers
                MRC     p15,0,r0,c0,c0,0                ; Read ID code
                ANDS    r0,r0,#0xF << 20                ; Is this a rev0 device?
                BEQ     rev0_skip3                      ; Yes: skip
                LDMDB   r1!,{r2-r3}                     ; Load
                MCR     p15,0,r3,c10,c2,1               ; Normal Memory Remap

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