📄 arm1136-shutdownmode-example_c.s
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; save the TCMs' contents.
; If your code runs on a system that never has TCMs, or you do
; not want to preserve the TCM contents, you can remove this
; section of code.
; This code assumes that both TCMs have flat address mappings:
; the virtual address of the base of each TCM is the same as the
; physical base address of that TCM. This assumption allows the
; code to get the TCM base address from the TCM Region register.
; If this assumption is not true, you must change the code to
; obtain the virtual address for the base of each TCM by a
; different method.
MRC p15,0,r0,c11,c0,0 ; Read DMA ID & Status
CMP r0,#3 ; Do we have a DMA?
BNE no_TCMsave ; No: skip TCM save
MRC p15,0,r2,c9,c1,0 ; D TCM Region
TST r2,#1 ; D TCM enabled?
BEQ no_DTCMsave ; No: skip D TCM save
TST r2,#1 << 1 ; D TCM is SmartCache?
BNE no_DTCMsave ; Yes: skip D TCM save
BIC r3,r2,#0xFF ; Get base address
ANDS r4,r2,#0x7C ; Get TCM size: is it 0?
BEQ no_DTCMsave ; Yes: skip D TCM save
MOV r4,r4,LSR #2 ; Move TCM size to LSBs
MOV r5,#0xF << 5 ; Addr bits [15:12] mask
BIC r3,r3,r5,LSL r4 ; Mask invalid addr bits
MOV r6,#1 << 9
MOV r6,r6,LSL r4 ; Get TCM size in bytes
ADD r7,r3,r6 ; Base addr + TCM size
LDR r8,=DTCMSTORE ; Get save addr
MOV r9,#0
MCR p15,0,r9,c11,c2,0 ; Select DMA channel 0
; Note: you may wish to adjust the DMA Control reg setup below.
LDR r10,=0x58000803 ; Control
MCR p15,0,r10,c11,c4,0 ; Control Register
MCR p15,0,r3,c11,c5,0 ; Internal Start Address
MCR p15,0,r8,c11,c6,0 ; External Start Address
MCR p15,0,r7,c11,c7,0 ; Internal End Address
MRC p15,0,r11,c13,c0,1 ; Read Context ID
MCR p15,0,r11,c11,c15,0 ; DMA Context ID
MCR p15,0,r0,c11,c3,1 ; Start DMA channel 0
no_DTCMsave
MRC p15,0,r2,c9,c1,1 ; I TCM Region
TST r2,#1 ; I TCM enabled?
BEQ no_ITCMsave ; No: skip I TCM save
TST r2,#1 << 1 ; I TCM is SmartCache?
BNE no_ITCMsave ; Yes: skip I TCM save
BIC r3,r2,#0xFF ; Get base address
ANDS r4,r2,#0x7C ; Get TCM size: is it 0?
BEQ no_ITCMsave ; Yes: skip I TCM save
MOV r4,r4,LSR #2 ; Move TCM size to LSBs
MOV r5,#0xF << 5 ; Addr bits [15:12] mask
BIC r3,r3,r5,LSL r4 ; Mask invalid addr bits
MOV r6,#1 << 9
MOV r6,r6,LSL r4 ; Get TCM size in bytes
ADD r7,r3,r6 ; Base addr + TCM size
LDR r8,=ITCMSTORE ; Get save addr
MOV r9,#1
MCR p15,0,r9,c11,c2,0 ; Select DMA channel 1
; Note: you may wish to adjust the DMA Control reg setup below.
LDR r10,=0xD8000803 ; Control
MCR p15,0,r10,c11,c4,0 ; Control Register
MCR p15,0,r3,c11,c5,0 ; Internal Start Address
MCR p15,0,r8,c11,c6,0 ; External Start Address
MCR p15,0,r7,c11,c7,0 ; Internal End Address
MRC p15,0,r11,c13,c0,1 ; Read Context ID
MCR p15,0,r11,c11,c15,0 ; DMA Context ID
MCR p15,0,r0,c11,c3,1 ; Start DMA channel 1
no_ITCMsave
no_TCMsave
; NB - Jazelle-DBX registers (CP14) were not forgotten. They
; should not be saved or restored by this routine. The
; Virtual Machine should be relied upon to re-initialize
; Jazelle-DBX state.
; Save lockdown region of TLB
LDR r0,=0x80000000
MCR p15,5,r0,c15,c4,2 ; Read lockdown entry 0
MRC p15,5,r2,c15,c5,2 ; Read Main TLB VA
MRC p15,5,r3,c15,c6,2 ; Read Main TLB PA
MRC p15,5,r4,c15,c7,2 ; Read Main TLB Attr
ADD r0,r0,#1
MCR p15,5,r0,c15,c4,2 ; Read lockdown entry 1
MRC p15,5,r5,c15,c5,2 ; Read Main TLB VA
MRC p15,5,r6,c15,c6,2 ; Read Main TLB PA
MRC p15,5,r7,c15,c7,2 ; Read Main TLB Attr
ADD r0,r0,#1
MCR p15,5,r0,c15,c4,2 ; Read lockdown entry 2
MRC p15,5,r8,c15,c5,2 ; Read Main TLB VA
MRC p15,5,r9,c15,c6,2 ; Read Main TLB PA
MRC p15,5,r10,c15,c7,2 ; Read Main TLB Attr
ADD r0,r0,#1
MCR p15,5,r0,c15,c4,2 ; Read lockdown entry 3
MRC p15,5,r11,c15,c5,2 ; Read Main TLB VA
MRC p15,5,r12,c15,c6,2 ; Read Main TLB PA
MRC p15,5,r13,c15,c7,2 ; Read Main TLB Attr
STMIA r1!,{r2-r13} ; Save
ADD r0,r0,#1
MCR p15,5,r0,c15,c4,2 ; Read lockdown entry 4
MRC p15,5,r2,c15,c5,2 ; Read Main TLB VA
MRC p15,5,r3,c15,c6,2 ; Read Main TLB PA
MRC p15,5,r4,c15,c7,2 ; Read Main TLB Attr
ADD r0,r0,#1
MCR p15,5,r0,c15,c4,2 ; Read lockdown entry 5
MRC p15,5,r5,c15,c5,2 ; Read Main TLB VA
MRC p15,5,r6,c15,c6,2 ; Read Main TLB PA
MRC p15,5,r7,c15,c7,2 ; Read Main TLB Attr
ADD r0,r0,#1
MCR p15,5,r0,c15,c4,2 ; Read lockdown entry 6
MRC p15,5,r8,c15,c5,2 ; Read Main TLB VA
MRC p15,5,r9,c15,c6,2 ; Read Main TLB PA
MRC p15,5,r10,c15,c7,2 ; Read Main TLB Attr
ADD r0,r0,#1
MCR p15,5,r0,c15,c4,2 ; Read lockdown entry 7
MRC p15,5,r11,c15,c5,2 ; Read Main TLB VA
MRC p15,5,r12,c15,c6,2 ; Read Main TLB PA
MRC p15,5,r13,c15,c7,2 ; Read Main TLB Attr
STMIA r1!,{r2-r13} ; Save
; Save the state of any memory-mapped peripherals that are
; powered down in shutdown mode.
; For example: the validation trickbox registers
; Replace this code with your own code to save the state of
; your memory-mapped peripherals.
TB_BASE EQU 0x13000000 ; Trickbox base address
LDR r0,=TB_BASE
LDR r2,[r0,#0x64] ; Trickbox abort addr
LDR r3,[r0,#0x44] ; Trickbox abort range 1
LDR r4,[r0,#0x40] ; Trickbox abort range 2
STMIA r1!,{r2-r4} ; Save
; Enable access to all coprocessors to save coproc & VFP state
; You can omit this if you have no coprocessors and no VFP
LDR r0,=0xFFFFFFFF ; Enable all coprocs
MCR p15,0,r0,c1,c0,2 ; Write coproc acc ctrl
; If we have a VFP coprocessor, save the VFP system regs and
; register bank.
; This code checks if the VFP is present by reading the
; coprocessor access control reg bits 23-20. If your code runs
; on a system that never has a VFP, you can remove this code.
; If your system always has a VFP, you can remove the check.
MRC p15,0,r0,c1,c0,2 ; Coproc access ctrl
ANDS r0,r0,#0xF << 20 ; VFP present?
BEQ no_VFP ; No - skip VFP save
FMRX r2,FPEXC ; VFP Exception
ORR r0,r2,#1 << 30 ; Enable VFP
FMXR FPEXC,r0 ; Write VFP Exception
FMRX r3,FPSCR ; VFP Status & Control
; This is done for cases where a pending VFP exception is taken on the
; previous "FMRX r3,FPSCR" instruction. If exception is taken, the
; old value in FPEXC is cleared. So reading FPEXC again.
FMRX r6,FPEXC
AND r2,r2,r6
FMRX r4,FPINST ; VFP Instruction
FMRX r5,FPINST2 ; VFP Instruction 2
STMIA r1!,{r2-r5} ; Save
FSTMIAX r1!,{d0-d15} ; Save VFP register bank
no_VFP
; Save the registers of all other coprocessors.
; As all coprocessors are different, we cannot write generic
; code here to save the registers of any coprocessor. If you
; have coprocessors other than the VFP, write your own code to
; save all of their registers to memory. Otherwise, remove this
; section of code.
; The example code here saves the validation generic
; coprocessors p4 & p5.
; Note: you can test for the presence of coprocessors by reading
; the appropriate bits of the coprocessor access control reg,
; but you still need to know what state must be saved for each
; individual coprocessor present in the system.
STC p4,c0,[r1],#4 ; Save coproc p4 regs
STC p4,c1,[r1],#4
STC p4,c2,[r1],#4
STC p4,c3,[r1],#4
STC p4,c4,[r1],#4
STC p4,c5,[r1],#4
STC p4,c6,[r1],#4
STC p4,c7,[r1],#4
STC p4,c8,[r1],#4
STC p4,c9,[r1],#4
STC p4,c10,[r1],#4
STC p4,c11,[r1],#4
STC p4,c12,[r1],#4
STC p4,c13,[r1],#4
STC p4,c14,[r1],#4
STC p4,c15,[r1],#4
STC p5,c0,[r1],#4 ; Save coproc p5 regs
STC p5,c1,[r1],#4
STC p5,c2,[r1],#4
STC p5,c3,[r1],#4
STC p5,c4,[r1],#4
STC p5,c5,[r1],#4
STC p5,c6,[r1],#4
STC p5,c7,[r1],#4
STC p5,c8,[r1],#4
STC p5,c9,[r1],#4
STC p5,c10,[r1],#4
STC p5,c11,[r1],#4
STC p5,c12,[r1],#4
STC p5,c13,[r1],#4
STC p5,c14,[r1],#4
STC p5,c15,[r1],#4
; Save the Performance Monitor registers
; Note that performance monitor counts will be restarted from
; these saved values on exiting shutdown mode, but not
; immediately, so the counts of events may not be correct.
MRC p15,0,r2,c15,c12,0 ; Performance mon ctrl
MRC p15,0,r3,c15,c12,1 ; Cycle counter
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