📄 arm1136-dormantmode-example_c.s
字号:
; The dormant mode exit code restores all required state in the correct order
; (generally the opposite order from that in which it was saved).
; You must make some modifications to this code as explained by the comments
; within it. When all state is restored, the dormant mode exit code restores
; the original CPSR, thus entering System mode (as dormant mode entry was
; called in System mode), and returns to the instruction after the the
; original call to the dormant mode entry code, using the following
; instruction:
; MOV pc,r14
; This assumes that the dormant mode entry code was called in System mode
; using an instruction of the form:
; BL dormant_entry
; Information about the dormant mode entry code is given at the start of that
; code.
EXPORT dormant_exit
dormant_exit
; Assume we are in a privileged mode.
; Enter system mode and ensure interrupts are disabled
CPSID aif,#MODE_SYS
; Load the address at the end of the state save memory region
LDR r1,dormant_end
; It is optional whether the Main TLB RAM remains powered up in Dormant mode.
; If it is powered up in Dormant mode in your implementation, restore the Main
; TLB master valid bits.
[ TLB_POWERED
; The Main TLB is fixed size so the number of TLB master valid
; bits is fixed at 64 i.e. 2 registers.
LDMDB r1!,{r2-r3} ; Load
MCR p15,5,r3,c15,c14,1 ; TLB master valid 1
MCR p15,5,r2,c15,c14,0 ; TLB master valid 0
]
; If TCMs were enabled as SmartCache, restore the SmartCache
; master valid bits and the TCM region registers.
; If TCMs are not enabled as SmartCache, we do not need to
; restore the SmartCache master valid bits, just the TCM region
; regs.
; This code checks if TCMs were enabled as SmartCache.
; If your code runs on a system that never has TCMs, you can
; remove this code; if your system has TCMs and always uses
; SmartCache, you can remove the check; if your system has TCMs
; and never uses SmartCache, you can remove this code except
; for the restoring of the TCM region regs.
; Note: saving and restoring the TCM region regs on a system
; with no TCMs has no effect, and is easier and quicker than
; testing if we have TCMs.
; Restore the SmartCache master valid registers
; Number of registers to restore depends on the TCM size:
; 4k TCM : restore reg 0
; 8k : 0
; 16k : 0-1
; 32k : 0-3
; 64k : 0-7
; Here we get the TCM sizes from the restored TCM region reg.
; If you know that your TCM sizes are fixed you can remove
; the checking and just restore the regs you need.
; Alternatively you can restore all regs 0-7 regardless of the
; TCM size - restoring unused regs has no effect. However,
; this impacts the performance due to extra MCRs and reads.
; Note: we must restore the TCM region regs before the
; SmartCache master valid bits, as a write to a TCM region reg
; automatically clears all SmartCache master valid bits for that
; TCM.
; I SmartCache master valid bits
LDR r10,[r1,#-4]! ; Load I TCM Region
MCR p15,0,r10,c9,c1,1 ; I TCM Region
TST r10,#1 << 1 ; SmartCache?
BEQ no_ISC_rst ; No: skip valid bits
AND r0,r10,#7 << 2 ; I TCM size in [4:2]
CMP r0,#7 << 2 ; I TCM = 64k?
LDMHSDB r1!,{r6-r9} ; Load
MCRHS p15,3,r9,c15,c10,7 ; I SC master valid 7
MCRHS p15,3,r8,c15,c10,6 ; I SC master valid 6
MCRHS p15,3,r7,c15,c10,5 ; I SC master valid 5
MCRHS p15,3,r6,c15,c10,4 ; I SC master valid 4
CMP r0,#6 << 2 ; I TCM >= 32k?
LDMHSDB r1!,{r4-r5} ; Load
MCRHS p15,3,r5,c15,c10,3 ; I SC master valid 3
MCRHS p15,3,r4,c15,c10,2 ; I SC master valid 2
CMP r0,#5 << 2 ; I TCM >= 16k?
LDRHS r3,[r1,#-4]! ; Load
MCRHS p15,3,r3,c15,c10,1 ; I SC master valid 1
LDR r2,[r1,#-4]! ; Load
MCR p15,3,r2,c15,c10,0 ; I SC master valid 0
no_ISC_rst
; D SmartCache master valid bits
LDR r10,[r1,#-4]! ; Load D TCM Region
MCR p15,0,r10,c9,c1,0 ; D TCM Region
TST r10,#1 << 1 ; SmartCache?
BEQ no_DSC_rst ; No: skip valid bits
AND r0,r10,#7 << 2 ; D TCM size in [4:2]
CMP r0,#7 << 2 ; D TCM = 64k?
LDMHSDB r1!,{r6-r9} ; Load
MCRHS p15,3,r9,c15,c14,7 ; D SC master valid 7
MCRHS p15,3,r8,c15,c14,6 ; D SC master valid 6
MCRHS p15,3,r7,c15,c14,5 ; D SC master valid 5
MCRHS p15,3,r6,c15,c14,4 ; D SC master valid 4
CMP r0,#6 << 2 ; D TCM >= 32k?
LDMHSDB r1!,{r4-r5} ; Load
MCRHS p15,3,r5,c15,c14,3 ; D SC master valid 3
MCRHS p15,3,r4,c15,c14,2 ; D SC master valid 2
CMP r0,#5 << 2 ; D TCM >= 16k?
LDRHS r3,[r1,#-4]! ; Load
MCRHS p15,3,r3,c15,c14,1 ; D SC master valid 1
LDR r2,[r1,#-4]! ; Load
MCR p15,3,r2,c15,c14,0 ; D SC master valid 0
no_DSC_rst
; Restore the cache master valid registers
; Number of registers to restore depends on the cache size:
; 4k cache: restore reg 0
; 8k : 0
; 16k : 0-1
; 32k : 0-3
; 64k : 0-7
; Here we get the cache sizes from the cache type reg.
; If you know that your cache sizes are fixed you can remove
; the checking and just restore the regs you need.
; Alternatively you can restore all regs 0-7 regardless of the
; cache size - restoring unused regs has no effect. However,
; this impacts the performance due to extra MRCs and reads.
; I cache master valid bits
MRC p15,0,r0,c0,c0,1 ; Cache type
AND r10,r0,#7 << 6 ; Icache size in [8:6]
CMP r10,#7 << 6 ; Icache = 64k?
LDMHSDB r1!,{r6-r9} ; Load
MCRHS p15,3,r9,c15,c8,7 ; Icache master valid 7
MCRHS p15,3,r8,c15,c8,6 ; Icache master valid 6
MCRHS p15,3,r7,c15,c8,5 ; Icache master valid 5
MCRHS p15,3,r6,c15,c8,4 ; Icache master valid 4
CMP r10,#6 << 6 ; Icache >= 32k?
LDMHSDB r1!,{r4-r5} ; Load
MCRHS p15,3,r5,c15,c8,3 ; Icache master valid 3
MCRHS p15,3,r4,c15,c8,2 ; Icache master valid 2
CMP r10,#5 << 6 ; Icache >= 16k?
LDRHS r3,[r1,#-4]! ; Load
MCRHS p15,3,r3,c15,c8,1 ; Icache master valid 1
LDR r2,[r1,#-4]! ; Load
MCR p15,3,r2,c15,c8,0 ; Icache master valid 0
; D cache master valid bits
AND r10,r0,#7 << 18 ; Dcache size in [8:6]
CMP r10,#7 << 18 ; Dcache = 64k?
LDMHSDB r1!,{r6-r9} ; Load
MCRHS p15,3,r9,c15,c12,7 ; Dcache master valid 7
MCRHS p15,3,r8,c15,c12,6 ; Dcache master valid 6
MCRHS p15,3,r7,c15,c12,5 ; Dcache master valid 5
MCRHS p15,3,r6,c15,c12,4 ; Dcache master valid 4
CMP r10,#6 << 18 ; Dcache >= 32k?
LDMHSDB r1!,{r4-r5} ; Load
MCRHS p15,3,r5,c15,c12,3 ; Dcache master valid 3
MCRHS p15,3,r4,c15,c12,2 ; Dcache master valid 2
CMP r10,#5 << 18 ; Dcache >= 16k?
LDRHS r3,[r1,#-4]! ; Load
MCRHS p15,3,r3,c15,c12,1 ; Dcache master valid 1
LDR r2,[r1,#-4]! ; Load
MCR p15,3,r2,c15,c12,0 ; Dcache master valid 0
; If Dormant mode does not have its own static memory setup, restore memory
; system control registers from main memory.
; If it does have its own setup, set it up now.
[ :LNOT: DM_STATICMEM
; ARM1136 rev1 has two extra memory system registers
MRC p15,0,r0,c0,c0,0 ; Read ID code
ANDS r0,r0,#0xF << 20 ; Is this a rev0 device?
BEQ rev0_skip4 ; Yes: skip
LDMDB r1!,{r2-r3} ; Load
MCR p15,0,r3,c10,c2,1 ; Normal Memory Remap
MCR p15,0,r2,c10,c2,0 ; Primary Region Remap
rev0_skip4
LDMDB r1!,{r2-r9} ; Load
MCR p15,0,r9,c9,c0,1 ; I Cache Lockdown
MCR p15,0,r8,c9,c0,0 ; D Cache Lockdown
MCR p15,7,r7,c15,c1,0 ; TLB Debug Control
MCR p15,7,r6,c15,c0,0 ; Cache Debug Control
MCR p15,0,r5,c15,c2,4 ; PP Mem Remap
MCR p15,0,r4,c15,c2,2 ; DMA Mem Remap
MCR p15,0,r3,c15,c2,1 ; Instr Mem Remap
MCR p15,0,r2,c15,c2,0 ; Data Mem Remap
LDMDB r1!,{r2-r8} ; Load
MCR p15,0,r8,c13,c0,1 ; Context ID
MCR p15,0,r7,c13,c0,0 ; FCSE PID
MCR p15,0,r6,c3,c0,0 ; DAC
MCR p15,0,r5,c2,c0,2 ; TTBCR
MCR p15,0,r4,c2,c0,1 ; TTBR1
MCR p15,0,r3,c2,c0,0 ; TTBR0
MCR p15,0,r2,c1,c0,0 ; Control
|
; Now set up the static memory configuration for Dormant mode.
; This may involve writing TTBR regs to use new page tables, or remapping
; memory to write-back.
]
; Note: if you have a separate static memory setup for dormant mode,
; the above state will be restored later.
; Restore the Debug registers
MRC p14,0,r0,c0,c1,0 ; Read DSCR
ORR r0,r0,#1 << 15 ; Select & enable Debug
BIC r0,r0,#1 << 14 ; monitor mode
MCR p14,0,r0,c0,c1,0 ; Write DSCR
LDMDB r1!,{r2-r6} ; Load
MCR p14,0,r6,c0,c7,0 ; VTR
MCR p14,0,r5,c0,c1,7 ; WCR1
MCR p14,0,r4,c0,c0,7 ; WCR0
MCR p14,0,r3,c0,c1,6 ; WVR1
MCR p14,0,r2,c0,c0,6 ; WVR0
LDMDB r1!,{r2-r14} ; Load
MCR p14,0,r14,c0,c5,5 ; BCR5
MCR p14,0,r13,c0,c4,5 ; BCR4
MCR p14,0,r12,c0,c3,5 ; BCR3
MCR p14,0,r11,c0,c2,5 ; BCR2
MCR p14,0,r10,c0,c1,5 ; BCR1
MCR p14,0,r9,c0,c0,5 ; BCR0
MCR p14,0,r8,c0,c5,4 ; BVR5
MCR p14,0,r7,c0,c4,4 ; BVR4
MCR p14,0,r6,c0,c3,4 ; BVR3
MCR p14,0,r5,c0,c2,4 ; BVR2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -