📄 arm1176-shutdownmode-example_c.s
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BEQ TCM0_rst ; No: skip TCM 1 restore MOV r0,#1 MCR p15,0,r0,c9,c2,0 ; Select TCM bank 1 CMP r11,#2 ; 2 I TCMs? LDMEQDB r1!,{r8-r9} ; Save MCREQ p15,0,r9,c9,c1,3 ; I TCM 1 NS ctrl access MCREQ p15,0,r8,c9,c1,1 ; I TCM 1 Region CMP r10,#2 ; 2 D TCMs? LDMEQDB r1!,{r6-r7} ; Save MCREQ p15,0,r7,c9,c1,2 ; D TCM 1 NS ctrl access MCREQ p15,0,r6,c9,c1,0 ; D TCM 1 RegionTCM0_rst MOV r0,#0 MCR p15,0,r0,c9,c2,0 ; Select TCM bank 0 CMP r11,#0 ; >0 I TCMs? LDMNEDB r1!,{r4-r5} ; Save MCRNE p15,0,r5,c9,c1,3 ; I TCM 0 NS ctrl access MCRNE p15,0,r4,c9,c1,1 ; I TCM 0 Region CMP r10,#0 ; >0 D TCMs? LDMNEDB r1!,{r2-r3} ; Save MCRNE p15,0,r3,c9,c1,2 ; D TCM 0 NS ctrl access MCRNE p15,0,r2,c9,c1,0 ; D TCM 0 Regionend_TCM_rst ; If I and/or D TCM(s) are enabled we need to restore the contents of these ; TCM(s). This is done using the internal DMA engine (if present) to load the ; entire contents of the enabled TCM(s) from main memory. You must define ; virtual addresses to save the TCM contents to. These addresses must have ; valid page table entries that produce a physical address suitable for the ; DMA. These addresses are defined at the top of this file. ; If you wish to preserve the contents of TCMs but your system does not have ; the internal DMA engine, you must rewrite this code to use an external DMA ; engine or some other method to load the TCMs' contents. ; If your code runs on a system that never has TCMs, or you do not want to ; preserve the TCM contents, you can remove this section of code. ; This code assumes that all TCMs have flat address mappings: the virtual ; address of the base of each TCM is the same as the physical base address of ; that TCM. This assumption allows the code to get the TCM base address from ; the TCM Region register. If this assumption is not true, you must change the ; code to obtain the virtual address for the base of each TCM by a different ; method. MRC p15,0,r0,c11,c0,0 ; Read DMA ID & Status CMP r0,#3 ; Do we have a DMA? BNE end_TCMload ; No: skip TCM load MRC p15,0,r0,c0,c0,2 ; Read TCM Status MOV r12,r0,LSR #16 ; Get # D TCMs (0-2) AND r13,r0,#3 ; Get # I TCMs (0-2) ADDS r0,r12,r13 ; 0 TCMs in total? BEQ end_TCMload ; Skip TCM loadDTCM0load MOV r0,#0 MCR p15,0,r0,c9,c2,0 ; Select TCM bank 0 CMP r12,#0 ; >0 D TCMs? BEQ ITCM0load ; No: skip D TCM 0 load MRC p15,0,r2,c9,c1,0 ; D TCM 0 Region TST r2,#1 ; D TCM 0 enabled? BEQ ITCM0load ; No: skip D TCM 0 load BIC r3,r2,#0xFF ; Get base address AND r4,r2,#0x7C ; Get TCM size MOV r4,r4,LSR #2 ; Move TCM size to LSBs MOV r5,#0xF << 5 ; Addr bits [15:12] mask BIC r3,r3,r5,LSL r4 ; Mask invalid addr bits MOV r6,#1 << 9 MOV r6,r6,LSL r4 ; Get TCM size in bytes ADD r7,r3,r6 ; Base addr + TCM size LDR r8,=DTCM0STORE ; Get load addr MOV r9,#0 MCR p15,0,r9,c11,c2,0 ; Select DMA channel 0 ; Note: you may wish to adjust the DMA Control reg setup below. LDR r10,=0x18000803 ; Control MCR p15,0,r10,c11,c4,0 ; Control Register MCR p15,0,r3,c11,c5,0 ; Internal Start Address MCR p15,0,r8,c11,c6,0 ; External Start Address MCR p15,0,r7,c11,c7,0 ; Internal End Address MRC p15,0,r11,c13,c0,1 ; Read Context ID MCR p15,0,r11,c11,c15,0 ; DMA Context ID MCR p15,0,r0,c11,c3,1 ; Start DMA channel 0ITCM0load CMP r13,#0 ; >0 I TCMs? BEQ DTCM1load ; No: skip I TCM 0 load MRC p15,0,r2,c9,c1,1 ; I TCM 0 Region TST r2,#1 ; I TCM 0 enabled? BEQ DTCM1load ; No: skip I TCM 0 load BIC r3,r2,#0xFF ; Get base address AND r4,r2,#0x7C ; Get TCM size MOV r4,r4,LSR #2 ; Move TCM size to LSBs MOV r5,#0xF << 5 ; Addr bits [15:12] mask BIC r3,r3,r5,LSL r4 ; Mask invalid addr bits MOV r6,#1 << 9 MOV r6,r6,LSL r4 ; Get TCM size in bytes ADD r7,r3,r6 ; Base addr + TCM size LDR r8,=ITCM0STORE ; Get load addr MOV r9,#1 MCR p15,0,r9,c11,c2,0 ; Select DMA channel 1 ; Note: you may wish to adjust the DMA Control reg setup below. LDR r10,=0x98000803 ; Control MCR p15,0,r10,c11,c4,0 ; Control Register MCR p15,0,r3,c11,c5,0 ; Internal Start Address MCR p15,0,r8,c11,c6,0 ; External Start Address MCR p15,0,r7,c11,c7,0 ; Internal End Address MRC p15,0,r11,c13,c0,1 ; Read Context ID MCR p15,0,r11,c11,c15,0 ; DMA Context ID MCR p15,0,r0,c11,c3,1 ; Start DMA channel 1DTCM1load ORR r0,r12,r13 TST r0,#2 ; 2 I TCMs or 2 D TCMs? BEQ end_TCMload ; No: skip TCM 1 load MOV r0,#1 MCR p15,0,r0,c9,c2,0 ; Select TCM bank 1 CMP r12,#2 ; 2 D TCMs? BNE ITCM1load ; No: skip D TCM 1 load MRC p15,0,r2,c9,c1,0 ; D TCM 1 Region TST r2,#1 ; D TCM 1 enabled? BEQ ITCM1load ; No: skip D TCM 1 load BIC r3,r2,#0xFF ; Get base address AND r4,r2,#0x7C ; Get TCM size MOV r4,r4,LSR #2 ; Move TCM size to LSBs MOV r5,#0xF << 5 ; Addr bits [15:12] mask BIC r3,r3,r5,LSL r4 ; Mask invalid addr bits MOV r6,#1 << 9 MOV r6,r6,LSL r4 ; Get TCM size in bytes ADD r7,r3,r6 ; Base addr + TCM size LDR r8,=DTCM1STORE ; Get load addr MOV r9,#0 MCR p15,0,r9,c11,c2,0 ; Select DMA channel 0 ; We must wait until DMA channel 0 is idle or complete, in case ; saving D TCM 0 is still in progress.wait_DTCM1load MRC p15,0,r0,c11,c8,0 ; DMA Status AND r0,r0,#3 ; Get status bits CMP r0,#2_01 ; Channel queued? CMPNE r0,#2_10 ; Or channel running? BEQ wait_DTCM1load ; Yes - wait MCR p15,0,r0,c11,c3,2 ; Clear channel 0 ; Note: you may wish to adjust the DMA Control reg setup below. LDR r10,=0x18000803 ; Control MCR p15,0,r10,c11,c4,0 ; Control Register MCR p15,0,r3,c11,c5,0 ; Internal Start Address MCR p15,0,r8,c11,c6,0 ; External Start Address MCR p15,0,r7,c11,c7,0 ; Internal End Address MRC p15,0,r11,c13,c0,1 ; Read Context ID MCR p15,0,r11,c11,c15,0 ; DMA Context ID MCR p15,0,r0,c11,c3,1 ; Start DMA channel 0ITCM1load CMP r13,#2 ; 2 I TCMs? BNE end_TCMload ; No: skip I TCM 1 load MRC p15,0,r2,c9,c1,1 ; I TCM 1 Region TST r2,#1 ; I TCM 1 enabled? BEQ end_TCMload ; No: skip I TCM 1 load BIC r3,r2,#0xFF ; Get base address AND r4,r2,#0x7C ; Get TCM size MOV r4,r4,LSR #2 ; Move TCM size to LSBs MOV r5,#0xF << 5 ; Addr bits [15:12] mask BIC r3,r3,r5,LSL r4 ; Mask invalid addr bits MOV r6,#1 << 9 MOV r6,r6,LSL r4 ; Get TCM size in bytes ADD r7,r3,r6 ; Base addr + TCM size LDR r8,=ITCM1STORE ; Get load addr MOV r9,#1 MCR p15,0,r9,c11,c2,0 ; Select DMA channel 1 ; We must wait until DMA channel 1 is idle or complete, in case ; saving I TCM 0 is still in progress.wait_ITCM1load MRC p15,0,r0,c11,c8,0 ; DMA Status AND r0,r0,#3 ; Get status bits CMP r0,#2_01 ; Channel queued? CMPNE r0,#2_10 ; Or channel running? BEQ wait_ITCM1load ; Yes - wait MCR p15,0,r0,c11,c3,2 ; Clear channel 1 ; Note: you may wish to adjust the DMA Control reg setup below. LDR r10,=0x98000803 ; Control MCR p15,0,r10,c11,c4,0 ; Control Register MCR p15,0,r3,c11,c5,0 ; Internal Start Address MCR p15,0,r8,c11,c6,0 ; External Start Address MCR p15,0,r7,c11,c7,0 ; Internal End Address MRC p15,0,r11,c13,c0,1 ; Read Context ID MCR p15,0,r11,c11,c15,0 ; DMA Context ID MCR p15,0,r0,c11,c3,1 ; Start DMA channel 1end_TCMload ; Restore the Secure and Monitor Vector Base Address registers ; Also restore the Secure Configuration register (with the NS bit ; cleared) so that interrupts during this restore code will be ; handled correctly. LDMDB r1!,{r2-r4} ; Load MCR p15,0,r4,c1,c1,0 ; S Config (NS bit = 0) MCR p15,0,r3,c12,c0,1 ; Mon Vector Base Address MCR p15,0,r2,c12,c0,0 ; S Vector Base Address ; Restore the Debug registers MRC p14,0,r0,c0,c1,0 ; Read DSCR ORR r0,r0,#1 << 15 ; Select & enable Debug BIC r0,r0,#1 << 14 ; monitor mode MCR p14,0,r0,c0,c1,0 ; Write DSCR LDMDB r1!,{r2-r9} ; Load MCR p14,0,r9,c0,c11,0 ; DSMCR MCR p14,0,r8,c0,c10,0 ; DSCCR MCR p14,0,r7,c0,c7,0 ; VCR MCR p14,0,r6,c0,c6,0 ; WFAR MCR p14,0,r5,c0,c1,7 ; WCR1 MCR p14,0,r4,c0,c0,7 ; WCR0 MCR p14,0,r3,c0,c1,6 ; WVR1 MCR p14,0,r2,c0,c0,6 ; WVR0 LDMDB r1!,{r2-r14} ; Load MCR p14,0,r14,c0,c5,5 ; BCR5 MCR p14,0,r13,c0,c4,5 ; BCR4 MCR p14,0,r12,c0,c3,5 ; BCR3 MCR p14,0,r11,c0,c2,5 ; BCR2 MCR p14,0,r10,c0,c1,5 ; BCR1 MCR p14,0,r9,c0,c0,5 ; BCR0 MCR p14,0,r8,c0,c5,4 ; BVR5 MCR p14,0,r7,c0,c4,4 ; BVR4 MCR p14,0,r6,c0,c3,4 ; BVR3 MCR p14,0,r5,c0,c2,4 ; BVR⌨️ 快捷键说明
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