📄 arm1176-shutdownmode-example_c.s
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MCR p15,0,r0,c9,c2,0 ; Select TCM bank 0 CMP r10,#0 ; >0 D TCMs? MRCNE p15,0,r2,c9,c1,0 ; D TCM 0 Region MRCNE p15,0,r3,c9,c1,2 ; D TCM 0 NS ctrl access STMNEIA r1!,{r2-r3} ; Save CMP r11,#0 ; >0 I TCMs? MRCNE p15,0,r4,c9,c1,1 ; I TCM 0 Region MRCNE p15,0,r5,c9,c1,3 ; I TCM 0 NS ctrl access STMNEIA r1!,{r4-r5} ; Save ORR r0,r10,r11 TST r0,#2 ; 2 I TCMs or 2 D TCMs? BEQ end_TCM ; No: skip TCM 1 save MOV r0,#1 MCR p15,0,r0,c9,c2,0 ; Select TCM bank 1 CMP r10,#2 ; 2 D TCMs? MRCEQ p15,0,r6,c9,c1,0 ; D TCM 1 Region MRCEQ p15,0,r7,c9,c1,2 ; D TCM 1 NS ctrl access STMEQIA r1!,{r6-r7} ; Save CMP r11,#2 ; 2 I TCMs? MRCEQ p15,0,r8,c9,c1,1 ; I TCM 1 Region MRCEQ p15,0,r9,c9,c1,3 ; I TCM 1 NS ctrl access STMEQIA r1!,{r8-r9} ; Saveend_TCM ; Save Secure memory system control registers MRC p15,0,r2,c1,c0,0 ; S Control MRC p15,0,r3,c2,c0,0 ; S TTBR0 MRC p15,0,r4,c2,c0,1 ; S TTBR1 MRC p15,0,r5,c2,c0,2 ; S TTBCR MRC p15,0,r6,c3,c0,0 ; S DAC MRC p15,0,r7,c13,c0,0 ; S FCSE PID MRC p15,0,r8,c13,c0,1 ; S Context ID MRC p15,0,r9,c10,c2,0 ; S Primary Region Remap MRC p15,0,r10,c10,c2,1 ; S Normal Memory Remap MRC p15,0,r11,c15,c2,4 ; S PP Memory Remap MRC p15,0,r12,c9,c8,0 ; Cache Behavior Override STMIA r1!,{r2-r12} ; Save ; Note: we do not save Cache Lockdown registers, as we lose the ; data or instructions in the locked ways. For workarounds ; see the equivalent point in the shutdown mode restore code, ; and the shutdown mode documentation. ; Save the address at the end of the state saving. ; Save this at a known fixed address so we can restore from it. STR r1,shutdown_end ; Wait for any running DMA operations (to save the contents of ; TCMs) to complete MRC p15,0,r0,c11,c0,0 ; DMA Status - present CMP r0,#3 ; DMA present? BNE no_waitTCMsave ; No: skip waitwait_TCMsave MRC p15,0,r2,c11,c0,1 ; DMA Status - queued MRC p15,0,r3,c11,c0,2 ; DMA Status - running CMP r2,#0 ; Any channel queued? BNE wait_TCMsave ; Yes: wait CMP r3,#0 ; Any channel running? BNE wait_TCMsave ; Yes: wait ; Clear both DMA channels (assume no errors occurred) MOV r2,#0 MCR p15,0,r2,c11,c2,0 ; Select channel 0 MCR p15,0,r2,c11,c3,2 ; Clear channel 0 MOV r3, #1 MCR p15,0,r3,c11,c2,0 ; Select channel 1 MCR p15,0,r2,c11,c3,2 ; Clear channel 1no_waitTCMsave ; Disable interrupts to make it easier to clean the data cache CPSID if ; Disable interrupts ; Clean the entire data cache MRC p15,0,r2,c1,c0,1 ; Read Aux ctrl reg BIC r2,r2,#1 << 4 ; Enable clean D cache MCR p15,0,r2,c1,c0,1 ; Write Aux ctrl reg MCR p15,0,r0,c7,c10,0 ; Clean entire D cache ; Set up your power controller so that it will enter shutdown ; mode when it next sees STANDBYWFI macrocell output go high. ; When this occurs, the power controller must drive the ; ARM1176's reset inputs low and hold them low while it removes ; the power supply to the logic, but not the RAMs. ; When the power controller wishes to exit shutdown mode, it ; must drive the ARM1176's reset inputs low and hold them low ; while it restores the power supply to the ARM1176. When it ; de-asserts the reset inputs, the reset code must identify that ; it is coming out of shutdown mode and branch to the shutdown ; mode restore code to restore system state. ; The validation world uses a memory-mapped trickbox feature to ; model the power controller: LDR r1,=TB_BASE ; Set up the shutdown LDR r0,=0x800 ; mode trickbox feature STR r0,[r1,#0xA4] ; Drain the write buffer MCR p15,0,r0,c7,c10,4 ; Wait for interrupt (asserts STANDBYWFI macrocell output) MCR p15,0,r0,c7,c0,4quit_shutdown_entry ; We come here if either DMA channel has stopped with an error. ; Restore any registers we have changed and return. MCR p15,0,r3,c11,c2,0 ; Restore DMA channel no LDR r1,=SHUTDOWNSTORE ; Get state save addr LDR r2,[r1,#0xA0] ; Load TLB lockdown MCR p15,0,r2,c10,c0,0 ; Restore TLB lockdown LDR r2,[r1,#0x40] ; Load S Config MCR p15,0,r2,c1,c1,0 ; Restore S Config LDR r2,[r1,#0x3C] ; Load SPSR_mon MSR SPSR_cxsf,r2 ; Restore SPSR_mon LDMIA r1,{r0-r14} ; Restore r0-r14 (MON) MOV pc,r14 ; Return ; END OF SHUTDOWN MODE ENTRY CODE; Data poolshutdown_end DCD 0r0_store DCD 0 LTORG;*******************************************************************************;* Shutdown mode exit;******************************************************************************* ; This code assumes that the reset exception handler determines (by whatever ; means) that the reset is due to exiting shutdown mode, and the reset handler ; then branches (by any means) to this shutdown mode exit code. The reset ; handler does not need to configure the ARM1176 in any way before this. The ; shutdown mode exit code assumes that it is entered in a privileged mode. ; The shutdown mode exit code restores all required state in the correct order ; (generally the opposite order from that in which it was saved). ; You must make some modifications to this code as explained by the comments ; within it. When all state is restored, the shutdown mode exit code restores ; the original CPSR, thus entering System mode (as shutdown mode entry was ; called in System mode), and returns to the instruction after the the ; original call to the shutdown mode entry code, using the following ; instruction: ; MOV pc,r14 ; This assumes that the shutdown mode entry code was called in System mode ; using an instruction of the form: ; BL shutdown_entry ; Information about the shutdown mode entry code is given at the start of that ; code. EXPORT shutdown_exitshutdown_exit ; Assume we are in a Secure privileged mode (as at reset). ; Enter Monitor mode and ensure interrupts are disabled ; Note that we enter Monitor mode by modifying the CPSR ; directly, rather than relying on a SMI handler that may not ; be set up yet. CPSID aif,#MODE_MON ; Make sure that the NS bit is clear so we can restore secure ; versions of banked registers. MRC p15,0,r0,c1,c1,0 ; Read S Config BIC r0,r0,#1 ; Clear NS bit MCR p15,0,r0,c1,c1,0 ; Write S Config ; Load the address at the end of the state save memory region LDR r1,shutdown_end ; Note: we do not save and restore the Cache Lockdown registers. ; Powering down the cache RAMs in shutdown mode loses the ; contents of any locked cache ways, so there is no point ; locking ways that are now empty. ; If you use the cache lockdown features, and the locked ways ; and their contents are static, you can simply repeat the code ; that you used to fill and lock the cache ways. ; If cache way locking or the addresses that are locked into ; cache ways vary, you will have to define some way of indicating ; what is locked into cache ways, save this information on entry ; to shutdown mode, and use this information on exit from ; shutdown mode to refill and lock the cache ways. ; Restore Secure memory system control registers LDMDB r1!,{r2-r12} ; Load MCR p15,0,r12,c9,c8,0 ; Cache Behavior Override MCR p15,0,r11,c15,c2,4 ; S PP Memory Remap MCR p15,0,r10,c10,c2,1 ; S Normal Memory Remap MCR p15,0,r9,c10,c2,0 ; S Primary Region Remap MCR p15,0,r8,c13,c0,1 ; S Context ID MCR p15,0,r7,c13,c0,0 ; S FCSE PID MCR p15,0,r6,c3,c0,0 ; S DAC MCR p15,0,r5,c2,c0,2 ; S TTBCR MCR p15,0,r4,c2,c0,1 ; S TTBR1 MCR p15,0,r3,c2,c0,0 ; S TTBR0 MRS r4, CPSR MSR CPSR_f, #&20000000 MCR p15,0,r2,c1,c0,0 ; S Control MCR p15,0,r2,c7,c5,4 ; Prefetch flush DCI 0x950f07ee ; Pf flush inverted MSR CPSR_cxsf, r4 ; Restore TCM registers ; This code checks how many I and D TCMs are present by reading ; the TCM Status Register, and only restores registers for TCMs ; that exist. (Saving registers for non-existent TCMs does no ; harm as the writes to restore the values are ignored by the ; processor, but it takes longer.) If you know the number of ; TCMs in your system is constant, you can simplify or remove ; this code. MRC p15,0,r0,c0,c0,2 ; Read TCM Status MOV r10,r0,LSR #16 ; Get # D TCMs (0-2) AND r11,r0,#3 ; Get # I TCMs (0-2) ADDS r0,r10,r11 ; 0 TCMs in total? BEQ end_TCM_rst ; Skip TCM reg restore ORR r0,r10,r11 TST r0,#2 ; 2 I TCMs or 2 D TCMs?⌨️ 快捷键说明
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