📄 dispdrvr.c
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}
case 2:
{
BPP = 1;
break;
}
case 4:
{
BPP = 2;
break;
}
case 8:
{
BPP = 3;
break;
}
case 16:
{
BPP = 4;
break;
}
default:
{
BPP = 0;
RETAILMSG(1, (TEXT("Bad BPP setting!")));
break;
}
}
// assume LCLK =100Mhz (99.5) for PCD
switch (nDisplayType)
{
case LQ039Q2DS54:
{
v_pLcdRegs->LCCR0 = ( LCD_OUM | LCD_BM | LCD_QDM |
LCD_PAS | LCD_EFM | LCD_IUM |
LCD_SFM | LCD_LDM );
/* 240 + 10 + 25 + 40 = 395 pixel clocks per line (vals below have +1 done internally) */
v_pLcdRegs->LCCR1 = ( LCD_PPL(239) | LCD_HSW(13) |
LCD_ELW(2) | LCD_BLW(58));
/* 320 + 13 + 2 + 7 = 262 line clocks per frame (LPP and VSW have +1 done internally) */
v_pLcdRegs->LCCR2 = ( LCD_LPP(319) | LCD_VSW(2) |
LCD_EFW(0) | LCD_BFW(5) );
/* 16bpp. pixel clock divisor is (7+1)*2 = 16. 99.5238Mhz / 16 = 6.22Mhz pixel clock */
v_pLcdRegs->LCCR3 = ( LCD_BPP(4) | LCD_PCD(7) | LCD_ACB(1) | LCD_PCP );
// backlight
v_pPwm1Regs->PWMCTRL = 31;
v_pPwm1Regs->PWMDUTY = (512*75)/100;
v_pPwm1Regs->PWMPERVAL = 512;
}
break;
case LM8V31:
{
// Reconfigure the upper panel frame descriptors for dual panel operation by
// setting the DMA transfer length to half the size of the frame buffer
frameDescriptorCh0fd1->LDCMD = frameBufferSize >> 1;
frameDescriptorCh0fd2->LDCMD = frameBufferSize >> 1;
// Configure the lower panel frame descriptor for dual panel operation.
// Set the physical address of the frame descriptor
frameDescriptorCh1->FDADR = (DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_PHYSICAL);
// Set the physical address of the frame buffer
frameDescriptorCh1->FSADR = ((FRAME_BUFFER_0_BASE_PHYSICAL) + (frameBufferSize >> 1));
// Clear the frame ID
frameDescriptorCh1->FIDR = 0;
// Set the DMA transfer length to half the ize of the frame buffer
frameDescriptorCh1->LDCMD = frameBufferSize >> 1;
// Store the physical address of this frame descriptor in the frame descriptor
frameDescriptorCh1->PHYSADDR = frameDescriptorCh1->FDADR;
// FBR1 is cleared and is not used in this implementation
v_pLcdRegs->FBR1 = 0;
// Load the contents of FDADR1 with the physical address of this frame descriptor
v_pLcdRegs->FDADR1 = frameDescriptorCh1->FDADR;
// Configure the TMED dithering engine
// Use the magic number described in the Cotulla EAS, 0x00AA5500;
v_pLcdRegs->TRGBR = ( LCD_TRS(0x00) | LCD_TGS(0x55) | LCD_TBS(0xAA) );
// Use the magic number described in the Cotulla EAS, 0x0000754F;
v_pLcdRegs->TCR = ( LCD_TM2S | LCD_TM1S | LCD_TM2En | LCD_TM1En |
LCD_TVBS(0x04) | LCD_THBS(0x05) | LCD_TSCS(0x03) |
LCD_TED );
v_pLcdRegs->LCCR0 = ( LCD_SDS | LCD_LDM | LCD_SFM | LCD_IUM |
LCD_EFM | LCD_PDD(0x01) | LCD_BM);
v_pLcdRegs->LCCR1 = ( LCD_PPL(0x27F) | LCD_HSW(0x02) |
LCD_ELW(0x03) | LCD_BLW(0x03) );
v_pLcdRegs->LCCR2 = ( LCD_LPP(0xef) | LCD_VSW(0x01) |
LCD_EFW(0x00) | LCD_BFW(0x00) );
v_pLcdRegs->LCCR3 = ( LCD_PCD(10) | LCD_ACB(0xff) |
LCD_PCP | LCD_BPP(BPP) );
}
break;
case LM057QCTT03:
{
// Configure the TMED dithering engine
// Use the magic number described in the Cotulla EAS, 0x00AA5500;
v_pLcdRegs->TRGBR = ( LCD_TRS(0x00) | LCD_TGS(0x55) | LCD_TBS(0xAA) );
// Use the magic number described in the Cotulla EAS, 0x0000754F;
v_pLcdRegs->TCR = ( LCD_TM2S | LCD_TM1S | LCD_TM2En | LCD_TM1En |
LCD_TVBS(0x04) | LCD_THBS(0x05) | LCD_TSCS(0x03) |
LCD_TED );
v_pLcdRegs->LCCR0 = ( LCD_LDM | LCD_SFM | LCD_IUM |
LCD_EFM | LCD_PDD(0x01) | LCD_BM );
v_pLcdRegs->LCCR1 = ( LCD_PPL(0x13F) | LCD_HSW(0x02) |
LCD_ELW(0x03) | LCD_BLW(0x03) );
v_pLcdRegs->LCCR2 = ( LCD_LPP(0xef) | LCD_VSW(0x01) |
LCD_EFW(0x00) | LCD_BFW(0x00) );
v_pLcdRegs->LCCR3 = ( LCD_PCD(23) | LCD_ACB(0x10) |
LCD_PCP | LCD_BPP(BPP) );
}
break;
case TFTQVGA:
{
v_pLcdRegs->LCCR0 = ( LCD_LDM | LCD_SFM | LCD_IUM |
LCD_EFM | LCD_PAS | LCD_BM);
v_pLcdRegs->LCCR1 = ( LCD_PPL(0x13F) | LCD_HSW(0x01) |
LCD_ELW(0x03) | LCD_BLW(0x33) );
v_pLcdRegs->LCCR2 = ( LCD_LPP(0xef) | LCD_VSW(0x02) |
LCD_EFW(0x04) | LCD_BFW(0x04) );
v_pLcdRegs->LCCR3 = ( LCD_PCD(7) | LCD_BPP(BPP) |
LCD_PCP | LCD_VSP | LCD_HSP);
}
break;
case LQ64D341: // 176x220 Stinger display
{
v_pLcdRegs->LCCR0 = ( LCD_LDM | LCD_SFM | LCD_IUM |
LCD_EFM | LCD_PAS | LCD_BM);
v_pLcdRegs->LCCR1 = ( LCD_PPL(0xAF) | LCD_HSW(0x02) |
LCD_ELW(0x7B) | LCD_BLW(0x03) );
v_pLcdRegs->LCCR2 = ( LCD_LPP(0xdb) | LCD_VSW(0x01) |
LCD_EFW(0x02) | LCD_BFW(0x00) );
v_pLcdRegs->LCCR3 = ( LCD_PCD(12) | LCD_BPP(BPP) |
LCD_VSP | LCD_HSP | LCD_PCP |
LCD_OEP);
}
break;
default:
{
RETAILMSG(1, (TEXT("No display type detected!")));
}
break;
}
}
void InitCursor()
{
gDrawCursorFlag = FALSE;
gCursorRect.left = (DispDrvr_cxScreen - CURSOR_XSIZE) >> 1;
gCursorRect.right = gCursorRect.left + CURSOR_XSIZE;
gCursorRect.top = (DispDrvr_cyScreen - CURSOR_YSIZE) >> 1;
gCursorRect.bottom = gCursorRect.top + CURSOR_YSIZE;
gxHot = gyHot = 0;
memset ((BYTE *)gCursorMask, 0xFF, sizeof(gCursorMask));
}
BOOL MapVirtualAddress()
{
DMA_ADAPTER_OBJECT Adapter;
PHYSICAL_ADDRESS PhysAddr;
Adapter.ObjectSize = sizeof (DMA_ADAPTER_OBJECT);
Adapter.InterfaceType = Internal;
Adapter.BusNumber = 0;
g_DisplayBaseVirtual = (DWORD)HalAllocateCommonBuffer(&Adapter, DISPLAY_BUFFER_SIZE, &PhysAddr, FALSE);
g_DisplayBasePhysical = PhysAddr.LowPart;
if (!g_DisplayBaseVirtual)
{
Cleanup();
return FALSE;
}
if (v_pLcdRegs == NULL)
{
PhysAddr.QuadPart = PXA255_BASE_REG_PA_LCD;
v_pLcdRegs = (volatile LCD_REG_T *) MmMapIoSpace(PhysAddr, 0x400, FALSE);
}
if (v_pClkRegs == NULL)
{
PhysAddr.QuadPart = PXA255_BASE_REG_PA_CLK;
v_pClkRegs = (volatile CLK_REG_T *) MmMapIoSpace(PhysAddr, 0x400, FALSE);
}
if (v_pPwm1Regs == NULL)
{
PhysAddr.QuadPart = PXA255_BASE_REG_PA_PWM1;
v_pPwm1Regs = (volatile PWM_REG_T *) MmMapIoSpace(PhysAddr, 0x400, FALSE);
}
if (v_pOstRegs == NULL)
{
PhysAddr.QuadPart = PXA255_BASE_REG_PA_OST;
v_pOstRegs = (volatile OST_REG_T *) MmMapIoSpace(PhysAddr, 0x400, FALSE);
}
if (!v_pLcdRegs || !v_pClkRegs || !v_pPwm1Regs || !v_pOstRegs)
{
DEBUGMSG(TRUE, (TEXT("ERROR: Failed to allocate LCD/PWM/OST register resources.\r\n")));
Cleanup();
return(FALSE);
}
frameDescriptorCh0fd1 = (volatile LCD_FRAME_DESCRIPTOR_T *)(DMA_CHANNEL_0_FRAME_DESCRIPTOR_BASE_VIRTUAL);
frameDescriptorCh0fd2 = (volatile LCD_FRAME_DESCRIPTOR_T *)(DMA_CHANNEL_0_ALT_FRAME_DESCRIPTOR_BASE_VIRTUAL);
frameDescriptorCh1 = (volatile LCD_FRAME_DESCRIPTOR_T *)(DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_VIRTUAL);
frameDescriptorPalette = (volatile LCD_FRAME_DESCRIPTOR_T *)(PALETTE_FRAME_DESCRIPTOR_BASE_VIRTUAL);
v_pPaletteBuffer = (volatile LCD_PALETTE_T *)(PALETTE_BUFFER_BASE_VIRTUAL);
// If your version of WinCE.NET supports VirtualSetAttributes(), apply the bufferable setting as above.
{
PVOID pPhysAddr;
unsigned offset, size;
pPhysAddr = (PVOID)(FRAME_BUFFER_0_BASE_PHYSICAL);
size = frameBufferSize*NUM_FRAME_BUFFERS;
offset = (unsigned)pPhysAddr & (0x1000 - 1);
size += (offset ? 0x1000 : 0);
pPhysAddr = (PVOID)((unsigned)pPhysAddr - offset);
if (size >= 1024*1024*2)
{
gFrameBuffer = (PBYTE)VirtualAlloc(NULL,size,MEM_RESERVE,PAGE_NOACCESS);
}
else
{
gFrameBuffer = (PBYTE)VirtualAlloc(NULL,1024*1024*2,MEM_RESERVE,PAGE_NOACCESS);
}
if (!VirtualCopy(gFrameBuffer, (LPVOID)((unsigned long)pPhysAddr >> 8), size, (PAGE_READWRITE | PAGE_NOCACHE | PAGE_PHYSICAL)))
{
gFrameBuffer = NULL;
}
else
{
gFrameBuffer += offset;
}
}
if (!gFrameBuffer)
{
Cleanup();
return (FALSE);
}
// Set the bufferable bit attribute to the frame buffer to enable write coalescing
// This setting achieves highest performance when drawing to the frame buffer.
VirtualSetAttributes(gFrameBuffer, frameBufferSize*NUM_FRAME_BUFFERS, 4, 4, NULL);
gBlankFrameBuffer = (PBYTE) VirtualAlloc(0, frameBufferSize, MEM_RESERVE | MEM_COMMIT,PAGE_READWRITE);
if (!gBlankFrameBuffer)
{
Cleanup();
return (FALSE);
}
return (TRUE);
}
// Free all the global memory resources
void Cleanup(void)
{
DMA_ADAPTER_OBJECT Adapter;
PHYSICAL_ADDRESS PhysAddr;
if (v_pLcdRegs)
{
VirtualFree((PVOID)v_pLcdRegs,0,MEM_RELEASE);
v_pLcdRegs = NULL;
}
if (v_pClkRegs)
{
VirtualFree((PVOID)v_pClkRegs,0,MEM_RELEASE);
v_pLcdRegs = NULL;
}
if (v_pPwm1Regs)
{
VirtualFree((PVOID)v_pPwm1Regs,0,MEM_RELEASE);
v_pLcdRegs = NULL;
}
if (v_pOstRegs)
{
VirtualFree((PVOID)v_pOstRegs,0,MEM_RELEASE);
v_pOstRegs = NULL;
}
if (gFrameBuffer)
{
VirtualFree((PVOID)gFrameBuffer,0,MEM_RELEASE);
gFrameBuffer = NULL;
}
Adapter.ObjectSize = sizeof (DMA_ADAPTER_OBJECT);
Adapter.InterfaceType = Internal;
Adapter.BusNumber = 0;
PhysAddr.HighPart = 0;
PhysAddr.LowPart = g_DisplayBasePhysical;
HalFreeCommonBuffer(&Adapter, DISPLAY_BUFFER_SIZE, PhysAddr, (void *)g_DisplayBaseVirtual, FALSE);
}
void DispDrvrPowerHandler(BOOL bOff)
{
if (bOff)
{
DisableLCDController();
}
else
{
// Copy the original frame buffer back in.
CopyFrameBuffer(FALSE);
// Initialize the GPIO registers for proper LCD Controller operation
// LCDSetupGPIOs();
// Initialize the LCD Controller and Board Control Register
InitLCDController();
// Clear LCD Controller status register
LCDClearStatusReg();
// Enable the LCD controller
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