📄 lan91c111.h
字号:
// Copyright (c) David Vescovi. All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
/*
*
* Copyright (c) Standard MicroSystems Corporation. All Rights Reserved.
*
* LAN91C111 Driver for Windows CE .NET
*
* Revision History
*_______________________________________________________________________________
* Author Date Version Description
*_______________________________________________________________________________
* Pramod Bhardwaj 6/18/2002 0.1 Beta Release
* Pramod Bhardwaj 7/15/2002 1.0 Release
* Pramod Bhardwaj 1/22/2003 1.1 Removed some platform dependencies
* Pramod Bhardwaj 4/15/2003 2.0 Added support for alloc interrupt
*_______________________________________________________________________________
*
*Description
* Hardware specific and driver datastructure declarations
*
*/
#ifndef __LAN91C111_ADAPTER__
#define __LAN91C111_ADAPTER__
#include <NDIS.H>
//NDIS Version Declaration
#ifdef NDIS50_MINIPORT
#define DRIVER_NDIS_MAJOR_VERSION 5
#define DRIVER_NDIS_MINOR_VERSION 0
#else
#define DRIVER_NDIS_MAJOR_VERSION 4
#define DRIVER_NDIS_MINOR_VERSION 0
#endif
#define DRIVER_NDIS_VERSION ((DRIVER_NDIS_MAJOR_VERSION << 8) + DRIVER_NDIS_MINOR_VERSION)
#define DRIVER_BUILD_NUM 1040804
#ifdef DEBUG
#define ZONE_LAN91 DEBUGZONE(0)
#define ZONE_INIT DEBUGZONE(1)
#define ZONE_RX DEBUGZONE(2)
#define ZONE_TX DEBUGZONE(3)
#define ZONE_INTR DEBUGZONE(4)
#define ZONE_INDICATERX DEBUGZONE(5)
#define ZONE_INDICATETX DEBUGZONE(6)
#define ZONE_OID DEBUGZONE(7)
#define ZONE_POWER DEBUGZONE(8)
#define ZONE_MEDIASTATE DEBUGZONE(9)
#define ZONE_SET DEBUGZONE(13)
#define ZONE_ERROR DEBUGZONE(15)
#endif
//---------------MINIPORT PACKET RELATED--------------------------
//The MINIPORT Packet structure. One per active send request.
typedef struct _MINIPORT_PACKET
{
struct _MINIPORT_PACKET *Next; // Next packet on queue.
UCHAR PacketNumber;// Adapter Packet number.
USHORT PacketRange;
} MINIPORT_PACKET;
#define MINIPORT_PACKET_SIZE sizeof(MINIPORT_PACKET)
//The MINIPORT packet queue structur and macros
typedef struct _MINIPORT_PACKET_QUE
{
MINIPORT_PACKET *First; // First packet on queue or 0
MINIPORT_PACKET *Last; // Last packet on queue or &First
} MINIPORT_PACKET_QUE;
#define MAC_PACKET_QUE_SIZE sizeof(MAC_PACKET_QUE)
//The MAC receive context structure.
typedef struct _MAC_RECEIVE_CONTEXT
{
UINT Range; // Packet size.
USHORT *PacketData; // User data.
} MAC_RECEIVE_CONTEXT;
#define MAC_RECEIVE_CONTEXT_SIZE sizeof(MAC_RECEIVE_CONTEXT)
//Hardware packet representation.
typedef struct _SMC_PACK_HEADER
{
USHORT Status;
USHORT Range;
} SMC_PACK_HEADER;
#define SMC_PACK_HEADER_SIZE sizeof(SMC_PACK_HEADER)
//Clear packet queue macro.
#define ClearPacketQue(Que) {(Que).First = (MINIPORT_PACKET *) 0; \
(Que).Last = (MINIPORT_PACKET *) &(Que).First;} \
//Test for empty queue macro.
#define IsPacketQueEmpty(Que) (((Que).First) == (MINIPORT_PACKET *) 0)
//Add a packet to queue macro.
#define QuePacket(Que, _Packet) {MINIPORT_PACKET *__Last = (Que).Last; \
_Packet->Next = (MINIPORT_PACKET *) 0; \
__Last->Next = (Que).Last = _Packet;}
//Remove a packet from queue macro.
#define DequePacket(Que, Packet) {Packet = (Que).First; \
if(((Que).First = Packet->Next) == (MINIPORT_PACKET *) 0) \
(Que).Last = (MINIPORT_PACKET *) &(Que).First;}
//Sneak a look at the packet at the head of the queue macro.
#define PeekQue(Que, _Packet) {_Packet = (Que).First;}
#define MAC_ADDRESS_SIZE 6
typedef struct _SMSC_NETWORK_ADDRESS
{
UCHAR Address[MAC_ADDRESS_SIZE]; // Network address
} SMSC_NETWORK_ADDRESS;
//----------------------------------------------------------------
#define SMSC_32BIT_RW 1
//Multicast Table Entry Structure
#define MAX_MULTICAST_ADDRESS 128
typedef struct
{
UINT MulticastTableEntryCount;
UCHAR MulticastTableEntry[MAX_MULTICAST_ADDRESS * ETH_LENGTH_OF_ADDRESS];
} MULTICAST_TABLE;
#define TOTAL_BUFFER_SIZE 0x2000
#define MAX_LOOKAHEAD_SIZE 1514
#define LOOK_AHEAD_BUFFER_SIZE 2048
#define MINIPORT_ADAPTER_SIZE sizeof(MINIPORT_ADAPTER)
#define MAX_FRAME_DATA_SIZE 1500
#define MAX_FRAME_SIZE ((USHORT)1514)
#define MIN_FRAME_SIZE 14
#define MIN_LEGAL_FRAME_SIZE 64
#define ETHERNET_HEADER_SIZE 14
#define MAC_ADDRESS_SIZE 6
#define MAX_MULTICAST_ADDRESS 128
#define PTR_WAIT 5 // Loop count waiting after pointer load
#define AUTO_NEGOTIATION 0xFF
#define DEFAULT_VALUE 0xFE
#define FULL_DUPLEX 0x01
#define HALF_DUPLEX 0x00
#define SPEED10 100000
#define SPEED100 1000000
#define DEFAULT_IO_BASE 0x300 // Platform Specific
#define DEFAULT_IRQ 10 // Platform Specific
#define DEFAULT_MEDIA 0 // Default media type
#define CHIPID_LAN91C111 9
#define CHIPREV_LAN91C111_REVA 0
#define CHIPREV_LAN91C111_REVB 1
//--------------------- DRIVER STRUCTURE --------------------------------
#pragma pack(16)
typedef struct _MINIPORT_ADAPTER
{
NDIS_HANDLE AdapterHandle;
ULONG IOBase; // Platform Specific - type might have to be changed to accomodate platform specific values
BOOLEAN IsPortRegistered; // I/O Port registere with NdisMRegisterIORage (...)
NDIS_MINIPORT_INTERRUPT InterruptInfo; // From NdisMRegisterInterrupt(..)
USHORT InterruptLevel; // IRQ in use
BOOLEAN IsInterruptSet; // Attached to interrupt using NdisMRegisterInterrupt(...)
USHORT InterruptVector;
BOOLEAN Auto_Negotiation;
USHORT BusType;
USHORT BusNumber;
USHORT ConfigReg; // Config register to be output
USHORT ChipID; // Chip ID
USHORT ChipRev; // Chip Revision
USHORT *LookAheadBuffer; // Pointer to lookahead buffer
USHORT State; // Current state of the Adapter..
NDIS_OID LookAhead; // Max lookahead size
UINT Speed; // Speed ?? 10/100
UCHAR Duplex; // Duplex ?? FDX/HDX
UCHAR MACAddress[6]; // Current Station address
UCHAR HashTable[8]; // Multicast hash bits
USHORT RCR; // Updated Receive Control Register.
USHORT TCR; // Updated Transmit Control Register.
USHORT CtrlRegister;
USHORT LinkStatus; // Link Status
BOOLEAN NeedIndComplete; // Recieve Complete indication
BOOLEAN RCVBroadcast; // If set recvs broadcasts.
BOOLEAN RCVAllMulticast; // Rcv All multicasts.
BOOLEAN PromiscuousMode;
MULTICAST_TABLE MulticastTable; // Multicast Table
BOOLEAN TxResPending; // When set, NDISMResourceAvailable should be called
MINIPORT_PACKET_QUE AckPending; // Waiting completion intr
PUCHAR TxBuffer; // Pointer to the TX Copy buffer
MINIPORT_PACKET_QUE AllocPending;
BOOLEAN AllocIntPending;
//Required Statistics.
UINT Stat_TxOK;
UINT Stat_RxOK;
UINT Stat_TxError;
UINT Stat_RxError;
UINT Stat_RxOvrn;
UINT Stat_AlignError;
UINT Stat_SingleColl;
UINT Stat_MultiColl;
}MINIPORT_ADAPTER, *PMINIPORT_ADAPTER, *PSMSC_ADAPTER;
//----------------- LAN91C111 Chip Specific Registry Declarations ---------
#define LAN91C111_CHIPID 9
#define BANK_SELECT 14 // Offset in IO space to Bank select
#define BANK_ID_MASK 0xff00 // Mask constant part of bank register
#define BANK_UPPER 0x3300 // Constant value for upper byte of bank register
#define BANK_MASK (BANK_UPPER | 3)
//Bank 0 Registers
#define BANK0_TCR 0 // Transmit control register
#define BANK0_STS 2 // EPH status register
#define BANK0_RCR 4 // Receive control register
#define BANK0_CTR 6 // Statistics counter register
#define BANK0_MIR 8 // Memory information register
#define BANK0_RPCR 10 // Memory configuration register
#define BANK0_RES 12 // Reserved
//Bank 1 Registers
#define BANK1_CONFIG 0 // Adapter configuration register
#define BANK1_BASE 2 // IO Base address
#define BANK1_IA0 4 // Current address bytes 0-1
#define BANK1_IA2 6 // Current address bytes 2-3
#define BANK1_IA4 8 // Current address bytes 4-5
#define BANK1_GEN 10 // General purpose
#define BANK1_CTL 12 // Control
//Bank 2 Registers
#define BANK2_MMU_CMD 0 // MMU command register
#define BANK2_PNR 2 // Packet Number Register (8 bit)
#define BANK2_ARR 3 // Allocation Result Register (8 bit)
#define BANK2_FIFOS 4
#define BANK2_TX_FIFO 4 // Transmit Fifo Port Register (8 bit)
#define BANK2_RX_FIFO 5 // Receive Fifo Port Register (8 bit)
#define BANK2_PTR 6 // Pointer Register
#define BANK2_DATA1 8 // Data Register
#define BANK2_DATA2 10 // Data Register
#define BANK2_INT_STS 12 // Interrupt Status Register (8 bit, Read Only)
#define BANK2_INT_ACK 12 // Interrupt Ack Register (8 bit, Write Only)
#define BANK2_INT_MSK 13 // Interrupt Mask Register (8 bit, Read/Write)
//Bank 3 Registers
#define BANK3_MT01 0 // Multicast Hash Table 0-1
#define BANK3_MT23 2 // Multicast Hash Table 2-3
#define BANK3_MT45 4 // Multicast Hash Table 4-5
#define BANK3_MT67 6 // Multicast Hash Table 6-7
#define BANK3_MGMT 8 // PHY management
#define BANK3_REV 10 // Chip Id/Revision
#define BANK3_ERCV 12 // Early receive configuration
//Masks for Transmit Control Register (BANK0_TCR)
#define TCR_SWFDUP 0x8000 // Full Duplex Switched Ethernet
#define TCR_EPH_LOOP 0x2000 // Loop at EPH block
#define TCR_STP_SQET 0x1000 // Stop xmit on SQET error
#define TCR_FDUPLX 0x0800 // Full duplex mode
#define TCR_MON_CSN 0x0400 // Monitor carrier
#define TCR_NO_CRC 0x0100 // Don't append CRC
#define TCR_PAD_EN 0x0080 // Pad short frames
#define TCR_FOR_COL 0x0004 // Force collision
#define TCR_LOOP 0x0002 // Local loopback
#define TCR_TX_ENA 0x0001 // Enable transmitter
//Masks for Receive Control Register (BANK0_RCR)
#define RCR_RESET 0x8000 // Software reset
#define RCR_FILT_CAR 0x4000 // Filter carrier for 12 bits
#define RCR_ABORT_ENB 0x2000 // Enables abort of receive when collision occurs
#define RCR_STRP_CRC 0x0200 // Strip CRC on received frames
#define RCR_RX_EN 0x0100 // Enable receiver
#define RCR_ALL_MUL 0x0004 // Accept all multicasts (no filtering)
#define RCR_PRMS 0x000 // Promiscuous mode
#define RCR_ABORT 0x0001 // Frame aborted (too long)
//Masks for Counter Register (BANK0_CTR)
#define CTR_EX_DFER 0xf000 // Number of excessively deferred xmits
#define CTR_DFER 0x0f00 // Number of deferred xmits
#define CTR_MCOL 0x00f0 // Number of multiple collisions
#define CTR_COL 0x000f // Number of single collisions
//Masks for Memory Information Register (BANK0_MIR)
#define MIR_FREE_MEM 0xff00 // Memory available (* 256 bytes)
#define MIR_MEM_SIZE 0x00ff // Memory size (* 256 bytes)
//Masks for Receive/Phy Control Register (BANK0_RPCR)
#define RPCR_SPEED 0x2000 // Speed select input
#define RPCR_DPLX 0x1000 // Duplex Select
#define RPCR_ANEG 0x0800 // Auto-Negotiation mode select
#define RPCR_LS2A 0x0080 // LED Select Signal Enable
#define RPCR_LS1A 0x0040 // LED Select Signal Enable
#define RPCR_LS0A 0x0020 // LED Select Signal Enable
//Adapter Configuration Register (BANK1_CONFIG)
#define CFG_EPH_POW_EN 0x8000 // =1 100mb port, =0 10mb port
#define CFG_NO_WAIT 0x1000 // No wait states
#define CFG_GPCNTRL 0x0400 // Full step signalling to AUI
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -