pxa255_i2c.h

老外的一个开源项目

// Copyright (c) David Vescovi.  All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation.  All rights reserved.
//------------------------------------------------------------------------------
//
//  Header: pxa255_i2c.h
//
//  Defines the i2c controler register layout and associated types and constants.
//
//------------------------------------------------------------------------------
#ifndef _PXA255_I2C_H_
#define _PXA255_I2C_H_

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
//
//  Type:  I2C_REG_T
//
//  Defines the control register layout.
//
//------------------------------------------------------------------------------

typedef struct
{
	VUINT32_T	IBMR;       //monitor register
	VUINT32_T	RSVD0;
	VUINT32_T	IDBR;       //data buffer register
	VUINT32_T	RSVD1;
	VUINT32_T	ICR;        //control register
	VUINT32_T	RSVD2;
	VUINT32_T	ISR;        //status register
	VUINT32_T	RSVD3;
	VUINT32_T	ISAR;       //slave address register
	VUINT32_T	RSVD4;
	VUINT32_T	I2CCR;      //clock count register
} I2C_REG_T, *PI2C_REG_T;


//
// ICR Bits
//
#define I2CR_MASTER_START       0x00000001  // indicate START to I2C
#define I2CR_MASTER_STOP        0x00000002  // indicate STOP after next data byte
#define I2CR_MASTER_NACKONRECV  0x00000004  // master sends NACK instead of ACK when byte received
#define I2CR_TRANSFER           0x00000008  // byte send/receive toggle
#define I2CR_MASTER_ABORT       0x00000010  // generate STOP without transmission
#define I2CR_MASTER_MODE        0x00000020  // operate as a master
#define I2CR_UNIT_ENABLE        0x00000040  // enable I2C unit
#define I2CR_GENCALL_DISABLE    0x00000080  // disable general call response
#define I2CR_ITEIE_ENABLE       0x00000100  // transmit empty
#define I2CR_IRFIE_ENABLE       0x00000200  // receive buffer full 
#define I2CR_BEIE_ENABLE        0x00000400  // bus error
#define I2CR_SSDIE_ENABLE       0x00000800  // slave stop detected
#define I2CR_ALDIE_ENABLE       0x00001000  // arbitration loss
#define I2CR_SADIE_ENABLE       0x00002000  // slave address match or general call
#define I2CR_UNIT_RESET         0x00004000  // reset unit
#define I2CR_MODE_400KBS        0x00008000  // fast mode

//
// ISR Bits
//
#define I2SR_MR_OR_ST           0x00000001  // unit is in master/receive or slave/transmit
#define I2SR_ACKNACK            0x00000002  // 
#define I2SR_UNITBUSY           0x00000004  // unit is busy
#define I2SR_BUSBUSY            0x00000008  // bus is busy
#define I2SR_SLAVESTOP          0x00000010  // STOP detected while in SLAVE mode
#define I2SR_ARBLOST            0x00000020  // master arbitration lost
#define I2SR_XMIT_EMPTY         0x00000040  // transmit buffer empty
#define I2SR_RECV_FULL          0x00000080  // receive buffer full
#define I2SR_TRANSREQ_GC        0x00000100  // valid if TRANSREQ set
#define I2SR_TRANSREQ           0x00000200  // received transmit request (slave mode)
#define I2SR_BUSERROR           0x00000400  // no ack from slave after byte sent


#if __cplusplus
}
#endif

#endif