pxa255_udc.h

老外的一个开源项目

// BEGIN USB UDC Endpoint 7 Control/Status Register (UDCCS7)
#define USB_UDCCS7_RFS					( 0x1 << 0 )	// Rx FIFO has 1 or more packets
#define USB_UDCCS7_RPC					( 0x1 << 1 )	// Rx packet received and err/stats valid
#define USB_UDCCS7_DME					( 0x1 << 3 )	// Send data received int after EOP
#define USB_UDCCS7_SST					( 0x1 << 4 )	// Stall handshake was sent
#define USB_UDCCS7_FST					( 0x1 << 5 )	// Issue stall handshake to OUT tokens
#define USB_UDCCS7_RNE					( 0x1 << 6 )	// Receive FIFO is not empty
#define USB_UDCCS7_RSP					( 0x1 << 7 )	// Short packet ready for reading

// USB UDC Endpoint 8 Control/Status Register (UDCCS8)
#define USB_UDCCS8_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS8_TPC					( 0x1 << 1 )	// Packet sent and err/status bits valid
#define USB_UDCCS8_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS8_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS8_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS8_TSP					( 0x1 << 7 )	// Short packet ready for transmission

// USB UDC Endpoint 9 Control/Status Register (UDCCS9)
#define USB_UDCCS9_RFS					( 0x1 << 0 )	// Rx FIFO has 1 or more packets
#define USB_UDCCS9_RPC					( 0x1 << 1 )	// Rx packet received and err/stats valid
#define USB_UDCCS9_ROF					( 0x1 << 2 )	// No receive overflow
#define USB_UDCCS9_DME					( 0x1 << 3 )	// Send data received int after EOP
#define USB_UDCCS9_SST					( 0x1 << 4 )	// Stall handshake was sent
#define USB_UDCCS9_FST					( 0x1 << 5 )	// Issue stall handshake to OUT tokens
#define USB_UDCCS9_RNE					( 0x1 << 6 )	// Receive FIFO is not empty
#define USB_UDCCS9_RSP					( 0x1 << 7 )	// Short packet ready for reading

// USB UDC Endpoint 10 Control/Status Register (UDCCS10)
#define USB_UDCCS10_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS10_TPC					( 0x1 << 1 )	// Packet sent and err/status bits valid
#define USB_UDCCS10_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS10_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS10_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS10_TSP					( 0x1 << 7 )	// Short packet ready for transmission

// USB UDC Endpoint 11 Control/Status Register (UDCCS11)
#define USB_UDCCS11_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS11_TPC 				( 0x1 << 1 )	// Packet sent and err/status bits valid
#define USB_UDCCS11_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS11_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS11_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS11_TSP					( 0x1 << 7 )	// Short packet ready for transmission

// USB UDC Endpoint 12 Control/Status Register (UDCCS12)
#define USB_UDCCS12_RFS					( 0x1 << 0 )	// Rx FIFO has 1 or more packets
#define USB_UDCCS12_RPC					( 0x1 << 1 )	// Rx packet received and err/stats valid
#define USB_UDCCS12_DME					( 0x1 << 3 )	// Send data received int after EOP
#define USB_UDCCS12_SST					( 0x1 << 4 )	// Stall handshake was sent
#define USB_UDCCS12_FST					( 0x1 << 5 )	// Issue stall handshake to OUT tokens
#define USB_UDCCS12_RNE					( 0x1 << 6 )	// Receive FIFO is not empty
#define USB_UDCCS12_RSP					( 0x1 << 7 )	// Short packet ready for reading

// USB UDC Endpoint 13 Control/Status Register (UDCCS13)
#define USB_UDCCS13_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS13_TPC					( 0x1 << 1 )    // Packet sent and err/status bits valid
#define USB_UDCCS13_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS13_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS13_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS13_TSP					( 0x1 << 7 )	// Short packet ready for transmission

// USB UDC Endpoint 14 Control/Status Register (UDCCS14)
#define USB_UDCCS14_RFS					( 0x1 << 0 )	// Rx FIFO has 1 or more packets
#define USB_UDCCS14_RPC					( 0x1 << 1 )	// Rx packet received and err/stats valid
#define USB_UDCCS14_ROF					( 0x1 << 2 )	// No receive overflow
#define USB_UDCCS14_DME					( 0x1 << 3 )	// Send data received int after EOP
#define USB_UDCCS14_SST					( 0x1 << 4 )	// Stall handshake was sent
#define USB_UDCCS14_FST					( 0x1 << 5 )	// Issue stall handshake to OUT tokens
#define USB_UDCCS14_RNE					( 0x1 << 6 )	// Receive FIFO is not empty
#define USB_UDCCS14_RSP					( 0x1 << 7 )	// Short packet ready for reading

// USB UDC Endpoint 15 Control/Status Register (UDCCS15)
#define USB_UDCCS15_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS15_TPC					( 0x1 << 1 )	// Packet sent and err/status bits valid
#define USB_UDCCS15_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS15_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS15_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS15_TSP					( 0x1 << 7 )	// Short packet ready for transmission

// USB UDC Interrupt Control Register 0 (UICR0)
#define USB_UICR0_IM0					( 0x1 << 0 )	// Endpoint 0 interrupt disabled
#define USB_UICR0_IM1					( 0x1 << 1 )	// Endpoint 1 Tx interrupt disabled
#define USB_UICR0_IM2					( 0x1 << 2 )	// Endpoint 2 Rx interrupt disabled
#define USB_UICR0_IM3					( 0x1 << 3 )	// Endpoint 3 Tx interrupt disabled
#define USB_UICR0_IM4					( 0x1 << 4 )	// Endpoint 4 Rx interrupt disabled
#define USB_UICR0_IM5					( 0x1 << 5 )	// Endpoint 5 Tx interrupt disabled
#define USB_UICR0_IM6					( 0x1 << 6 )	// Endpoint 6 Tx interrupt disabled
#define USB_UICR0_IM7					( 0x1 << 7 )	// Endpoint 7 Rx interrupt disabled

// BEGIN USB UDC Interrupt Control Register 1 (UICR1)
#define USB_UICR1_IM8					( 0x1 << 0 )	// Endpoint 8 Tx interrupt disabled
#define USB_UICR1_IM9					( 0x1 << 1 )	// Endpoint 9 Rx interrupt disabled
#define USB_UICR1_IM10					( 0x1 << 2 )	// Endpoint 10 Rx interrupt disabled
#define USB_UICR1_IM11					( 0x1 << 3 )	// Endpoint 11 Tx interrupt disabled
#define USB_UICR1_IM12					( 0x1 << 4 )	// Endpoint 12 Rx interrupt disabled
#define USB_UICR1_IM13					( 0x1 << 5 )	// Endpoint 13 Tx interrupt disabled
#define USB_UICR1_IM14					( 0x1 << 6 )	// Endpoint 14 Rx interrupt disabled
#define USB_UICR1_IM15					( 0x1 << 7 )	// Endpoint 15 Rx interrupt disabled

// USB UDC Status/Interrupt Register 0 (UISR0)
#define USB_UISR0_IR0					( 0x1 << 0 )	// Endpoint 0 needs service
#define USB_UISR0_IR1					( 0x1 << 1 )	// Endpoint 1 needs service
#define USB_UISR0_IR2					( 0x1 << 2 )	// Endpoint 2 needs service
#define USB_UISR0_IR3					( 0x1 << 3 )	// Endpoint 3 needs service
#define USB_UISR0_IR4					( 0x1 << 4 )	// Endpoint 4 needs service
#define USB_UISR0_IR5					( 0x1 << 5 )	// Endpoint 5 needs service
#define USB_UISR0_IR6					( 0x1 << 6 )	// Endpoint 6 needs service
#define USB_UISR0_IR7					( 0x1 << 7 )	// Endpoint 7 needs service

// USB UDC Status/Interrupt Register 1 (UISR1)
#define USB_UISR1_IR8					( 0x1 << 0 )	// Endpoint 8 needs service
#define USB_UISR1_IR9					( 0x1 << 1 )	// Endpoint 9 needs service
#define USB_UISR1_IR10					( 0x1 << 2 )	// Endpoint 10 needs service
#define USB_UISR1_IR11					( 0x1 << 3 )	// Endpoint 11 needs service
#define USB_UISR1_IR12					( 0x1 << 4 )	// Endpoint 12 needs service
#define USB_UISR1_IR13					( 0x1 << 5 )	// Endpoint 13 needs service
#define USB_UISR1_IR14					( 0x1 << 6 )	// Endpoint 14 needs service
#define USB_UISR1_IR15					( 0x1 << 7 )	// Endpoint 15 needs service


//
// UDC Control Register Macros (UDCCR)
//

//
// UDC Enable (UDE)
// 
// Mask for write 1 to clear bits in UDCCR
#define UDCCR_MASK					(USB_UDCCR_RSTIR | USB_UDCCR_SUSIR | USB_UDCCR_RESIR)
#define UDCCR_MWRITE( pReg, y )		((pReg) = (((pReg) & (~UDCCR_MASK)) | y))

#define UDCCR_UDE_ENABLE(pUDCCR)	(UDCCR_MWRITE(pUDCCR, USB_UDCCR_UDE))
#define UDCCR_UDE_DISABLE(pUDCCR)	((pUDCCR) = ((pUDCCR) & (~(UDCCR_MASK | USB_UDCCR_UDE))))

// Mask for write 1 to clear bits in UDCCS0
#define UDCCS0_MASK					(USB_UDCCS0_SST | USB_UDCCS0_OPR | USB_UDCCS0_SA)
#define UDCCS0_MWRITE( x, y )		(UDCCS0(x) = ((UDCCS0(x) & (~UDCCS0_MASK)) | y))

//
// Reset Interrupt Mask (REM)
//
#define UDCCR_REM_ENABLE(pUDCCR)	((pUDCCR) = ((pUDCCR) & (~(UDCCR_MASK | USB_UDCCR_REM))))
#define UDCCR_REM_DISABLE(pUDCCR)	(UDCCR_MWRITE(pUDCCR, USB_UDCCR_REM))

#define UDCCR_SRM_ENABLE(pUDCCR)    ((pUDCCR) = ((pUDCCR) & (~(UDCCR_MASK | USB_UDCCR_SRM))))
#define UDCCR_SRM_DISABLE(pUDCCR)   (UDCCR_MWRITE(pUDCCR, USB_UDCCR_SRM))

//
// Clear the Reset Interrupt request (write 1 to clear)
//
#define UDCCR_RSTIR_CLR(pUDCCR)     (UDCCR_MWRITE(pUDCCR, USB_UDCCR_RSTIR))
#define UDCCR_SUSIR_CLR(pUDCCR)     (UDCCR_MWRITE(pUDCCR, USB_UDCCR_SUSIR))
#define UDCCR_RESIR_CLR(pUDCCR)     (UDCCR_MWRITE(pUDCCR, USB_UDCCR_RESIR))



//------------------------------------------------------------------------------

#if __cplusplus
}
#endif

#endif