pxa255_udc.h

老外的一个开源项目

// Copyright (c) David Vescovi.  All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation.  All rights reserved.
//------------------------------------------------------------------------------
//
//  Header: pxa255_udc.h
//
//  Defines the Universal Serial Bus Device Controler (UCD) register layout 
//  and associated types and constants.
//
//------------------------------------------------------------------------------
#ifndef _PXA255_UCD_H_
#define _PXA255_UCD_H_

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
//
//  Type:  UDC_REG_T
//
//  Defines the RTC control register layout.
//
//------------------------------------------------------------------------------

typedef struct
{
    VUINT32_T		UDCCR;
    VUINT32_T		RSVD0[3];
    VUINT32_T		UDCCS0;
    VUINT32_T		UDCCS1;
    VUINT32_T		UDCCS2;
    VUINT32_T		UDCCS3;
    VUINT32_T		UDCCS4;
    VUINT32_T		UDCCS5;
    VUINT32_T		UDCCS6;
    VUINT32_T		UDCCS7;
    VUINT32_T		UDCCS8;
    VUINT32_T		UDCCS9;
    VUINT32_T		UDCCS10;
    VUINT32_T		UDCCS11;
    VUINT32_T		UDCCS12;     
    VUINT32_T		UDCCS13;     
    VUINT32_T		UDCCS14;     
    VUINT32_T		UDCCS15;     
    VUINT32_T		UICR0;         
    VUINT32_T		UICR1;     
    VUINT32_T		UISR0;     
    VUINT32_T		UISR1;     
    VUINT32_T		UFNHR;		//0x60
    VUINT32_T		UFNLR;		//0x64
    VUINT32_T		UBC2;    
    VUINT32_T		UBC4;    
    VUINT32_T		UBC7;    
    VUINT32_T		UBC9;
    VUINT32_T		UBC12;    
    VUINT32_T		UBC14;    
    VUINT32_T		UDDR0;      //0x80  
    VUINT32_T		RSVD3[7];
    VUINT32_T		UDDR5;      //0xa0  
    VUINT32_T		RSVD5[7];
    VUINT32_T		UDDR10;     //0xc0 
    VUINT32_T		RSVD6[7];
    VUINT32_T		UDDR15;     //0xe0 
    VUINT32_T		RSVD7[7];
    VUINT32_T		UDDR1;      //0x100 
    VUINT32_T		RSVD8[31];
    VUINT32_T		UDDR2;      //0x180
    VUINT32_T		RSVD9[31];
    VUINT32_T		UDDR3;      //0x200
    VUINT32_T		RSVD10[127];
    VUINT32_T		UDDR4;      //0x400
    VUINT32_T		RSVD11[127];
    VUINT32_T		UDDR6;      //0x600
    VUINT32_T		RSVD12[31];
    VUINT32_T		UDDR7;      //0x680
    VUINT32_T		RSVD13[31];
    VUINT32_T		UDDR8;      //0x700
    VUINT32_T		RSVD14[127];
    VUINT32_T		UDDR9;      //0x900
    VUINT32_T		RSVD15[127];
    VUINT32_T		UDDR11;     //0xb00
    VUINT32_T		RSVD16[31];
    VUINT32_T		UDDR12;     //0xb80
    VUINT32_T		RSVD17[31];
    VUINT32_T		UDDR13;     //0xc00
    VUINT32_T		RSVD18[127];
    VUINT32_T		UDDR14;     //0xe00
} UDC_REG_T, *PUDC_REG_T;


// USB UDC Control Register (UDCCR)
#define USB_UDCCR_UDE					( 0x1 << 0 )	// USB enabled
#define USB_UDCCR_UDA					( 0x1 << 1 )	// READ-ONLY: udc is active
#define USB_UDCCR_RSM					( 0x1 << 2 )	// Forces the usb out of suspend state
#define USB_UDCCR_RESIR					( 0x1 << 3 )	// UDC received resume signalling from host
#define USB_UDCCR_SUSIR					( 0x1 << 4 )	// UDC received	suspend signalling from host
#define USB_UDCCR_SRM					( 0x1 << 5 )	// Suspend/Resume interrupt disabled
#define USB_UDCCR_RSTIR					( 0x1 << 6 )	// Set when the host issues a UDC reset
#define USB_UDCCR_REM					( 0x1 << 7 )	// Reset interrupt disabled

// USB UDC Endpoint 0 Control/Status Register (UDCCS0)
#define USB_UDCCS0_OPR					( 0x1 << 0 )	// OUT packet to endpoint zero received
#define USB_UDCCS0_IPR					( 0x1 << 1 )	// Packet has been written to endpoint zero FIFO
#define USB_UDCCS0_FTF					( 0x1 << 2 )	// Flush the Tx FIFO
#define USB_UDCCS0_SST					( 0x1 << 4 )	// UDC sent stall handshake
#define USB_UDCCS0_FST					( 0x1 << 5 )	// Force the UDC to issue a stall handshake
#define USB_UDCCS0_RNE					( 0x1 << 6 )	// There is unread data in the Rx FIFO
#define USB_UDCCS0_SA					( 0x1 << 7 )	// Current packet in FIFO is part of USB setup command

// USB UDC Endpoint 1 Control/Status Register (UDCCS1)
#define USB_UDCCS1_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS1_TPC					( 0x1 << 1 )	// Packet sent and err/status bits valid
#define USB_UDCCS1_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS1_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS1_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS1_TSP					( 0X1 << 7 )	// Short packet ready for transmission

// USB UDC Endpoint 2 Control/Status Register (UDCCS2)
#define USB_UDCCS2_RFS					( 0x1 << 0 )	// Rx FIFO has 1 or more packets
#define USB_UDCCS2_RPC					( 0x1 << 1 )	// Rx packet received and err/stats valid
#define USB_UDCCS2_DME					( 0x1 << 3 )	// DMA Enable
#define USB_UDCCS2_SST					( 0x1 << 4 )	// Stall handshake was sent
#define USB_UDCCS2_FST					( 0x1 << 5 )	// Issue stall handshake to OUT tokens
#define USB_UDCCS2_RNE					( 0x1 << 6 )	// Receive FIFO is not empty
#define USB_UDCCS2_RSP					( 0x1 << 7 )	// Short packet ready for reading

// USB UDC Endpoint 3 Control/Status Register (UDCCS3)
#define USB_UDCCS3_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS3_TPC					( 0x1 << 1 )	// Packet sent and err/status bits valid
#define USB_UDCCS3_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS3_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS3_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS3_TSP					( 0x1 << 7 )	// Short packet ready for transmission

// USB UDC Endpoint 4 Control/Status Register (UDCCS4)
#define USB_UDCCS4_RFS					( 0x1 << 0 )	// Rx FIFO has 1 or more packets
#define USB_UDCCS4_RPC					( 0x1 << 1 )	// Rx packet received and err/stats valid
#define USB_UDCCS4_ROF					( 0x1 << 2 )	// No receive overflow
#define USB_UDCCS4_DME					( 0x1 << 3 )	// Send data received int after EOP
#define USB_UDCCS4_SST					( 0x1 << 4 )	// Stall handshake was sent
#define USB_UDCCS4_FST					( 0x1 << 5 )	// Issue stall handshake to OUT tokens
#define USB_UDCCS4_RNE					( 0x1 << 6 )	// Receive FIFO is not empty
#define USB_UDCCS4_RSP					( 0x1 << 7 )	// Short packet ready for reading

// USB UDC Endpoint 5 Control/Status Register (UDCCS5)
#define USB_UDCCS5_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS5_TPC					( 0x1 << 1 )	// Packet sent and err/status bits valid
#define USB_UDCCS5_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS5_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS5_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS5_TSP					( 0X1 << 7 )	// Short packet ready for transmission

// USB UDC Endpoint 6 Control/Status Register (UDCCS6)
#define USB_UDCCS6_TFS					( 0x1 << 0 )	// Tx FIFO has room for at least one packet
#define USB_UDCCS6_TPC					( 0x1 << 1 )	// Packet sent and err/status bits valid
#define USB_UDCCS6_TUR					( 0x1 << 3 )	// Tx FIFO experienced underrun
#define USB_UDCCS6_SST					( 0x1 << 4 )	// Write 1 to clear.  Stall was sent
#define USB_UDCCS6_FST					( 0x1 << 5 )	// Issue stall handshake
#define USB_UDCCS6_TSP					( 0X1 << 7 )	// Short packet ready for transmission