📄 pxa255_base_regs.inc
字号:
;Copyright (c) David Vescovi. All rights reserved.
;Part of Project DrumStix
;Windows Embedded Developers Interest Group (WE-DIG) community project.
;http://www.we-dig.org
;Copyright (c) Microsoft Corporation. All rights reserved.
;------------------------------------------------------------------------------
;
; File: pxa255_base_regs.inc
;
; Intel pxa255 register and physical address definitions.
;
;------------------------------------------------------------------------------
IF !:DEF: _pxa255regs_inc_
_pxa255_base_regs_inc_ EQU 1
;
; Peripheral registers base
;
PXA255_BASE_REG_PA_PERIPH EQU 0x40000000
;
; Peripheral register offsets
;
DMAC_OFFSET EQU 0x00000000 ; DMA CONTROLLER
FFUART_OFFSET EQU 0x00100000 ; Full-Feature UART
BTUART_OFFSET EQU 0x00200000 ; BlueTooth UART
I2C_OFFSET EQU 0x00301680 ; I2C
I2S_OFFSET EQU 0x00400000 ; I2S
AC97_OFFSET EQU 0x00500000 ; AC97
UDC_OFFSET EQU 0x00600000 ; UDC (usb client)
STUART_OFFSET EQU 0x00700000 ; Standard UART
ICP_OFFSET EQU 0x00800000 ; ICP (infrared)
RTC_OFFSET EQU 0x00900000 ; real time clock
OST_OFFSET EQU 0x00A00000 ; OS Timer
PWM0_OFFSET EQU 0x00B00000 ; PWM 0 (pulse-width mod)
PWM1_OFFSET EQU 0x00C00000 ; PWM 1 (pulse-width mod)
INTC_OFFSET EQU 0x00D00000 ; Interrupt controller
GPIO_OFFSET EQU 0x00E00000 ; GPIO
PWR_OFFSET EQU 0x00F00000 ; Power Manager and Reset Control
SSP_OFFSET EQU 0x01000000 ; SSP
MMC_OFFSET EQU 0x01100000 ; MMC
CLK_OFFSET EQU 0x01300000 ; Clock Manager
NSSP_OFFSET EQU 0x01400000 ; Network SSP
HWUART_OFFSET EQU 0x01600000 ; Hardware UART
LCD_OFFSET EQU 0x04000000 ; Hardware UART
MEMC_OFFSET EQU 0x08000000 ; Memory controler
;
; Peripheral-specific base addresses
;
; PCMCIA Slots 0,1
;
PXA255_BASE_REG_PA_PCMCIA_S0_IO EQU 0x20000000
PXA255_BASE_REG_PA_PCMCIA_S0_ATTR EQU 0x28000000
PXA255_BASE_REG_PA_PCMCIA_S0_CMN EQU 0x2C000000
PXA255_BASE_REG_PA_PCMCIA_S1_IO EQU 0x30000000
PXA255_BASE_REG_PA_PCMCIA_S1_ATTR EQU 0x38000000
PXA255_BASE_REG_PA_PCMCIA_S1_CMN EQU 0x3C000000
PXA255_BASE_REG_PA_DMAC EQU (PXA255_BASE_REG_PA_PERIPH + DMAC_OFFSET)
PXA255_BASE_REG_PA_FFUART EQU (PXA255_BASE_REG_PA_PERIPH + FFUART_OFFSET)
PXA255_BASE_REG_PA_BTUART EQU (PXA255_BASE_REG_PA_PERIPH + BTUART_OFFSET)
PXA255_BASE_REG_PA_I2C EQU (PXA255_BASE_REG_PA_PERIPH + I2C_OFFSET)
PXA255_BASE_REG_PA_I2S EQU (PXA255_BASE_REG_PA_PERIPH + I2S_OFFSET)
PXA255_BASE_REG_PA_AC97 EQU (PXA255_BASE_REG_PA_PERIPH + AC97_OFFSET)
PXA255_BASE_REG_PA_UDC EQU (PXA255_BASE_REG_PA_PERIPH + UDC_OFFSET)
PXA255_BASE_REG_PA_STUART EQU (PXA255_BASE_REG_PA_PERIPH + STUART_OFFSET)
PXA255_BASE_REG_PA_ICP EQU (PXA255_BASE_REG_PA_PERIPH + ICP_OFFSET)
PXA255_BASE_REG_PA_RTC EQU (PXA255_BASE_REG_PA_PERIPH + RTC_OFFSET)
PXA255_BASE_REG_PA_OST EQU (PXA255_BASE_REG_PA_PERIPH + OST_OFFSET)
PXA255_BASE_REG_PA_PWM0 EQU (PXA255_BASE_REG_PA_PERIPH + PWM0_OFFSET)
PXA255_BASE_REG_PA_PWM1 EQU (PXA255_BASE_REG_PA_PERIPH + PWM1_OFFSET)
PXA255_BASE_REG_PA_INTC EQU (PXA255_BASE_REG_PA_PERIPH + INTC_OFFSET)
PXA255_BASE_REG_PA_GPIO EQU (PXA255_BASE_REG_PA_PERIPH + GPIO_OFFSET)
PXA255_BASE_REG_PA_PWR EQU (PXA255_BASE_REG_PA_PERIPH + PWR_OFFSET)
PXA255_BASE_REG_PA_SSP EQU (PXA255_BASE_REG_PA_PERIPH + SSP_OFFSET)
PXA255_BASE_REG_PA_MMC EQU (PXA255_BASE_REG_PA_PERIPH + MMC_OFFSET)
PXA255_BASE_REG_PA_CLK EQU (PXA255_BASE_REG_PA_PERIPH + CLK_OFFSET)
PXA255_BASE_REG_PA_NSSP EQU (PXA255_BASE_REG_PA_PERIPH + NSSP_OFFSET)
PXA255_BASE_REG_PA_HWUART EQU (PXA255_BASE_REG_PA_PERIPH + HWUART_OFFSET)
PXA255_BASE_REG_PA_LCD EQU (PXA255_BASE_REG_PA_PERIPH + LCD_OFFSET)
PXA255_BASE_REG_PA_MEMC EQU (PXA255_BASE_REG_PA_PERIPH + MEMC_OFFSET)
;
; Relevant registers
;
;
; UART OFFSETS
;
THR_OFFSET EQU 0x0
RBR_OFFSET EQU 0x0
DLL_OFFSET EQU 0x0
IER_OFFSET EQU 0x4
DLH_OFFSET EQU 0x4
IIR_OFFSET EQU 0x8
FCR_OFFSET EQU 0x8
LCR_OFFSET EQU 0xC
MCR_OFFSET EQU 0x10
LSR_OFFSET EQU 0x14
MSR_OFFSET EQU 0x18
SPR_OFFSET EQU 0x1C
ISR_OFFSET EQU 0x20
FOR_OFFSET EQU 0x24 ;HW UART only
ABR_OFFSET EQU 0x28 ;HW UART only
ACR_OFFSET EQU 0x2C ;HW UART only
;
; FULL-FUNCTION UART
;
FFUART_THR EQU (PXA255_BASE_REG_PA_FFUART + THR_OFFSET)
FFUART_RBR EQU (PXA255_BASE_REG_PA_FFUART + RBR_OFFSET)
FFUART_DLL EQU (PXA255_BASE_REG_PA_FFUART + DLL_OFFSET)
FFUART_IER EQU (PXA255_BASE_REG_PA_FFUART + IER_OFFSET)
FFUART_DLH EQU (PXA255_BASE_REG_PA_FFUART + DLH_OFFSET)
FFUART_IIR EQU (PXA255_BASE_REG_PA_FFUART + IIR_OFFSET)
FFUART_FCR EQU (PXA255_BASE_REG_PA_FFUART + FCR_OFFSET)
FFUART_LCR EQU (PXA255_BASE_REG_PA_FFUART + LCR_OFFSET)
FFUART_MCR EQU (PXA255_BASE_REG_PA_FFUART + MCR_OFFSET)
FFUART_LSR EQU (PXA255_BASE_REG_PA_FFUART + LSR_OFFSET)
FFUART_MSR EQU (PXA255_BASE_REG_PA_FFUART + MSR_OFFSET)
FFUART_SPR EQU (PXA255_BASE_REG_PA_FFUART + SPR_OFFSET)
FFUART_ISR EQU (PXA255_BASE_REG_PA_FFUART + ISR_OFFSET)
;
; STANDARD UART
;
STUART_THR EQU (PXA255_BASE_REG_PA_STUART + THR_OFFSET)
STUART_RBR EQU (PXA255_BASE_REG_PA_STUART + RBR_OFFSET)
STUART_DLL EQU (PXA255_BASE_REG_PA_STUART + DLL_OFFSET)
STUART_IER EQU (PXA255_BASE_REG_PA_STUART + IER_OFFSET)
STUART_DLH EQU (PXA255_BASE_REG_PA_STUART + DLH_OFFSET)
STUART_IIR EQU (PXA255_BASE_REG_PA_STUART + IIR_OFFSET)
STUART_FCR EQU (PXA255_BASE_REG_PA_STUART + FCR_OFFSET)
STUART_LCR EQU (PXA255_BASE_REG_PA_STUART + LCR_OFFSET)
STUART_MCR EQU (PXA255_BASE_REG_PA_STUART + MCR_OFFSET)
STUART_LSR EQU (PXA255_BASE_REG_PA_STUART + LSR_OFFSET)
STUART_MSR EQU (PXA255_BASE_REG_PA_STUART + MSR_OFFSET)
STUART_SPR EQU (PXA255_BASE_REG_PA_STUART + SPR_OFFSET)
STUART_ISR EQU (PXA255_BASE_REG_PA_STUART + ISR_OFFSET)
;
; HARDWARE UART
;
HWUART_THR EQU (PXA255_BASE_REG_PA_HWUART + THR_OFFSET)
HWUART_RBR EQU (PXA255_BASE_REG_PA_HWUART + RBR_OFFSET)
HWUART_DLL EQU (PXA255_BASE_REG_PA_HWUART + DLL_OFFSET)
HWUART_IER EQU (PXA255_BASE_REG_PA_HWUART + IER_OFFSET)
HWUART_DLH EQU (PXA255_BASE_REG_PA_HWUART + DLH_OFFSET)
HWUART_IIR EQU (PXA255_BASE_REG_PA_HWUART + IIR_OFFSET)
HWUART_FCR EQU (PXA255_BASE_REG_PA_HWUART + FCR_OFFSET)
HWUART_LCR EQU (PXA255_BASE_REG_PA_HWUART + LCR_OFFSET)
HWUART_MCR EQU (PXA255_BASE_REG_PA_HWUART + MCR_OFFSET)
HWUART_LSR EQU (PXA255_BASE_REG_PA_HWUART + LSR_OFFSET)
HWUART_MSR EQU (PXA255_BASE_REG_PA_HWUART + MSR_OFFSET)
HWUART_SPR EQU (PXA255_BASE_REG_PA_HWUART + SPR_OFFSET)
HWUART_ISR EQU (PXA255_BASE_REG_PA_HWUART + ISR_OFFSET)
HWUART_FOR EQU (PXA255_BASE_REG_PA_HWUART + FOR_OFFSET)
HWUART_ABR EQU (PXA255_BASE_REG_PA_HWUART + ABR_OFFSET)
HWUART_ACR EQU (PXA255_BASE_REG_PA_HWUART + ACR_OFFSET)
;
; RTC MANAGER
;
RCNR_OFFSET EQU 0x0
RTAR_OFFSET EQU 0x4
RTSR_OFFSET EQU 0x8
RTTR_OFFSET EQU 0x8
RCNR EQU (PXA255_BASE_REG_PA_RTC + RCNR_OFFSET)
RTAR EQU (PXA255_BASE_REG_PA_RTC + RTAR_OFFSET)
RTSR EQU (PXA255_BASE_REG_PA_RTC + RTSR_OFFSET)
RTTR EQU (PXA255_BASE_REG_PA_RTC + RTTR_OFFSET)
;
; OS TIMER
;
OSMR0_OFFSET EQU 0x0
OSMR1_OFFSET EQU 0x4
OSMR2_OFFSET EQU 0x8
OSMR3_OFFSET EQU 0xC
OSCR_OFFSET EQU 0x10
OSSR_OFFSET EQU 0x14
OWER_OFFSET EQU 0x18
OIER_OFFSET EQU 0x1C
OSMR0 EQU (PXA255_BASE_REG_PA_OST + OSMR0_OFFSET)
OSMR1 EQU (PXA255_BASE_REG_PA_OST + OSMR1_OFFSET)
OSMR2 EQU (PXA255_BASE_REG_PA_OST + OSMR2_OFFSET)
OSMR3 EQU (PXA255_BASE_REG_PA_OST + OSMR3_OFFSET)
OSCR EQU (PXA255_BASE_REG_PA_OST + OSCR_OFFSET)
OSSR EQU (PXA255_BASE_REG_PA_OST + OSSR_OFFSET)
OWER EQU (PXA255_BASE_REG_PA_OST + OWER_OFFSET)
OIER EQU (PXA255_BASE_REG_PA_OST + OIER_OFFSET)
;
; INTERRUPT CONTROLLER
;
ICIP_OFFSET EQU 0x0
ICMR_OFFSET EQU 0x4
ICLR_OFFSET EQU 0x8
ICFP_OFFSET EQU 0xC
ICPR_OFFSET EQU 0x10
ICCR_OFFSET EQU 0x14
ICIP EQU (PXA255_BASE_REG_PA_INTC + ICIP_OFFSET)
ICMR EQU (PXA255_BASE_REG_PA_INTC + ICMR_OFFSET)
ICLR EQU (PXA255_BASE_REG_PA_INTC + ICLR_OFFSET)
ICFP EQU (PXA255_BASE_REG_PA_INTC + ICFP_OFFSET)
ICPR EQU (PXA255_BASE_REG_PA_INTC + ICPR_OFFSET)
ICCR EQU (PXA255_BASE_REG_PA_INTC + ICCR_OFFSET)
;
; GPIO
;
GPLR0_OFFSET EQU 0x0
GPLR1_OFFSET EQU 0x4
GPLR2_OFFSET EQU 0x8
GPDR0_OFFSET EQU 0xC
GPDR1_OFFSET EQU 0x10
GPDR2_OFFSET EQU 0x14
GPSR0_OFFSET EQU 0x18
GPSR1_OFFSET EQU 0x1C
GPSR2_OFFSET EQU 0x20
GPCR0_OFFSET EQU 0x24
GPCR1_OFFSET EQU 0x28
GPCR2_OFFSET EQU 0x2C
GRER0_OFFSET EQU 0x30
GRER1_OFFSET EQU 0x34
GRER2_OFFSET EQU 0x38
GFER0_OFFSET EQU 0x3C
GFER1_OFFSET EQU 0x40
GFER2_OFFSET EQU 0x44
GEDR0_OFFSET EQU 0x48
GEDR1_OFFSET EQU 0x4C
GEDR2_OFFSET EQU 0x50
GAFR0_L_OFFSET EQU 0x54
GAFR0_U_OFFSET EQU 0x58
GAFR1_L_OFFSET EQU 0x5C
GAFR1_U_OFFSET EQU 0x60
GAFR2_L_OFFSET EQU 0x64
GAFR2_U_OFFSET EQU 0x68
GPLR0 EQU (PXA255_BASE_REG_PA_GPIO + GPLR0_OFFSET)
GPLR1 EQU (PXA255_BASE_REG_PA_GPIO + GPLR1_OFFSET)
GPLR2 EQU (PXA255_BASE_REG_PA_GPIO + GPLR2_OFFSET)
GPDR0 EQU (PXA255_BASE_REG_PA_GPIO + GPDR0_OFFSET)
GPDR1 EQU (PXA255_BASE_REG_PA_GPIO + GPDR1_OFFSET)
GPDR2 EQU (PXA255_BASE_REG_PA_GPIO + GPDR2_OFFSET)
GPSR0 EQU (PXA255_BASE_REG_PA_GPIO + GPSR0_OFFSET)
GPSR1 EQU (PXA255_BASE_REG_PA_GPIO + GPSR1_OFFSET)
GPSR2 EQU (PXA255_BASE_REG_PA_GPIO + GPSR2_OFFSET)
GPCR0 EQU (PXA255_BASE_REG_PA_GPIO + GPCR0_OFFSET)
GPCR1 EQU (PXA255_BASE_REG_PA_GPIO + GPCR1_OFFSET)
GPCR2 EQU (PXA255_BASE_REG_PA_GPIO + GPCR2_OFFSET)
GRER0 EQU (PXA255_BASE_REG_PA_GPIO + GRER0_OFFSET)
GRER1 EQU (PXA255_BASE_REG_PA_GPIO + GRER1_OFFSET)
GRER2 EQU (PXA255_BASE_REG_PA_GPIO + GRER2_OFFSET)
GFER0 EQU (PXA255_BASE_REG_PA_GPIO + GFER0_OFFSET)
GFER1 EQU (PXA255_BASE_REG_PA_GPIO + GFER1_OFFSET)
GFER2 EQU (PXA255_BASE_REG_PA_GPIO + GFER2_OFFSET)
GEDR0 EQU (PXA255_BASE_REG_PA_GPIO + GEDR0_OFFSET)
GEDR1 EQU (PXA255_BASE_REG_PA_GPIO + GEDR1_OFFSET)
GEDR2 EQU (PXA255_BASE_REG_PA_GPIO + GEDR2_OFFSET)
GAFR0_L EQU (PXA255_BASE_REG_PA_GPIO + GAFR0_L_OFFSET)
GAFR0_U EQU (PXA255_BASE_REG_PA_GPIO + GAFR0_U_OFFSET)
GAFR1_L EQU (PXA255_BASE_REG_PA_GPIO + GAFR1_L_OFFSET)
GAFR1_U EQU (PXA255_BASE_REG_PA_GPIO + GAFR1_U_OFFSET)
GAFR2_L EQU (PXA255_BASE_REG_PA_GPIO + GAFR2_L_OFFSET)
GAFR2_U EQU (PXA255_BASE_REG_PA_GPIO + GAFR2_U_OFFSET)
;
; POWER MANAGER & RESET CONTROL
;
PMCR_OFFSET EQU 0x0
PSSR_OFFSET EQU 0x4
PSPR_OFFSET EQU 0x8
PWER_OFFSET EQU 0xC
PRER_OFFSET EQU 0x10
PFER_OFFSET EQU 0x14
PEDR_OFFSET EQU 0x18
PCFR_OFFSET EQU 0x1C
PGSR0_OFFSET EQU 0x20
PGSR1_OFFSET EQU 0x24
PGSR2_OFFSET EQU 0x28
RCSR_OFFSET EQU 0x30
PMCR EQU (PXA255_BASE_REG_PA_PWR + PMCR_OFFSET)
PSSR EQU (PXA255_BASE_REG_PA_PWR + PSSR_OFFSET)
PSPR EQU (PXA255_BASE_REG_PA_PWR + PSPR_OFFSET)
PWER EQU (PXA255_BASE_REG_PA_PWR + PWER_OFFSET)
PRER EQU (PXA255_BASE_REG_PA_PWR + PRER_OFFSET)
PFER EQU (PXA255_BASE_REG_PA_PWR + PFER_OFFSET)
PEDR EQU (PXA255_BASE_REG_PA_PWR + PEDR_OFFSET)
PCFR EQU (PXA255_BASE_REG_PA_PWR + PCFR_OFFSET)
PGSR0 EQU (PXA255_BASE_REG_PA_PWR + PGSR0_OFFSET)
PGSR1 EQU (PXA255_BASE_REG_PA_PWR + PGSR1_OFFSET)
PGSR2 EQU (PXA255_BASE_REG_PA_PWR + PGSR2_OFFSET)
RCSR EQU (PXA255_BASE_REG_PA_PWR + RCSR_OFFSET)
;
; CLK MANAGER
;
CCCR_OFFSET EQU 0x0
CKEN_OFFSET EQU 0x4
OSCC_OFFSET EQU 0x8
CCCR EQU (PXA255_BASE_REG_PA_CLK + CCCR_OFFSET)
CKEN EQU (PXA255_BASE_REG_PA_CLK + CKEN_OFFSET)
OSCC EQU (PXA255_BASE_REG_PA_CLK + OSCC_OFFSET)
; MEMC
;
MDCNFG_OFFSET EQU 0x0
MDREFR_OFFSET EQU 0x4
MSC0_OFFSET EQU 0x8
MSC1_OFFSET EQU 0xC
MSC2_OFFSET EQU 0x10
MECR_OFFSET EQU 0x14
SXLCR_OFFSET EQU 0x18
SXCNFG_OFFSET EQU 0x1C
FLYCNFG_OFFSET EQU 0x20
SXMRS_OFFSET EQU 0x24
MCMEM0_OFFSET EQU 0x28
MCMEM1_OFFSET EQU 0x2C
MCATT0_OFFSET EQU 0x30
MCATT1_OFFSET EQU 0x34
MCIO0_OFFSET EQU 0x38
MCIO1_OFFSET EQU 0x3C
MDMRS_OFFSET EQU 0x40
BOOT_DEF_OFFSET EQU 0x44
MDMRSLP_OFFSET EQU 0x58
SA1111CD_OFFSET EQU 0x64
MDCNFG EQU (PXA255_BASE_REG_PA_MEMC + MDCNFG_OFFSET)
MDREFR EQU (PXA255_BASE_REG_PA_MEMC + MDREFR_OFFSET)
MSC0 EQU (PXA255_BASE_REG_PA_MEMC + MSC0_OFFSET)
MSC1 EQU (PXA255_BASE_REG_PA_MEMC + MSC1_OFFSET)
MSC2 EQU (PXA255_BASE_REG_PA_MEMC + MSC2_OFFSET)
MECR EQU (PXA255_BASE_REG_PA_MEMC + MECR_OFFSET)
SXLCR EQU (PXA255_BASE_REG_PA_MEMC + SXLCR_OFFSET)
SXCNFG EQU (PXA255_BASE_REG_PA_MEMC + SXCNFG_OFFSET)
FLYCNFG EQU (PXA255_BASE_REG_PA_MEMC + FLYCNFG_OFFSET)
SXMRS EQU (PXA255_BASE_REG_PA_MEMC + SXMRS_OFFSET)
MCMEM0 EQU (PXA255_BASE_REG_PA_MEMC + MCMEM0_OFFSET)
MCMEM1 EQU (PXA255_BASE_REG_PA_MEMC + MCMEM1_OFFSET)
MCATT0 EQU (PXA255_BASE_REG_PA_MEMC + MCATT0_OFFSET)
MCATT1 EQU (PXA255_BASE_REG_PA_MEMC + MCATT1_OFFSET)
MCIO0 EQU (PXA255_BASE_REG_PA_MEMC + MCIO0_OFFSET)
MCIO1 EQU (PXA255_BASE_REG_PA_MEMC + MCIO1_OFFSET)
MDMRS EQU (PXA255_BASE_REG_PA_MEMC + MDMRS_OFFSET)
BOOT_DEF EQU (PXA255_BASE_REG_PA_MEMC + BOOT_DEF_OFFSET)
MDMRSLP EQU (PXA255_BASE_REG_PA_MEMC + MDMRSLP_OFFSET)
SA1111CD EQU (PXA255_BASE_REG_PA_MEMC + SA1111CD_OFFSET)
ENDIF ; !:DEF: _pxa255_base_regs_inc_
END
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -