pxa255_base_regs.h

老外的一个开源项目

// Copyright (c) David Vescovi.  All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation.  All rights reserved.
//------------------------------------------------------------------------------
//
//  File:  pxa255_base_regs.h
//
//  Intel pxa255 register and physical address definitions.
//
//------------------------------------------------------------------------------
#ifndef _pxa255_base_regs_h_
#define _pxa255_base_regs_h_

//
// Peripheral registers base
//
#define PXA255_BASE_REG_PA_PERIPH			0x40000000

//
// Peripheral register offsets
//
#define DMAC_OFFSET				0x00000000	// DMA CONTROLLER
#define FFUART_OFFSET			0x00100000	// Full-Feature UART
#define BTUART_OFFSET			0x00200000	// BlueTooth UART
#define I2C_OFFSET				0x00301680	// I2C
#define I2S_OFFSET				0x00400000	// I2S
#define AC97_OFFSET				0x00500000	// AC97
#define UDC_OFFSET				0x00600000	// UDC (usb client)
#define STUART_OFFSET			0x00700000	// Standard UART
#define ICP_OFFSET				0x00800000	// ICP (infrared)
#define RTC_OFFSET				0x00900000	// real time clock
#define OST_OFFSET				0x00A00000	// OS Timer
#define PWM0_OFFSET				0x00B00000	// PWM 0 (pulse-width mod)
#define PWM1_OFFSET				0x00C00000	// PWM 1 (pulse-width mod)
#define INTC_OFFSET				0x00D00000	// Interrupt controller
#define GPIO_OFFSET				0x00E00000	// GPIO
#define PWR_OFFSET				0x00F00000	// Power Manager and Reset Control
#define SSP_OFFSET				0x01000000	// SSP
#define MMC_OFFSET				0x01100000	// MMC
#define CLK_OFFSET				0x01300000	// Clock Manager
#define NSSP_OFFSET				0x01400000	// Network SSP
#define HWUART_OFFSET			0x01600000	// Hardware UART
#define LCD_OFFSET				0x04000000	// Hardware UART
#define MEMC_OFFSET				0x08000000	// Memory controler

//
// Peripheral-specific base addresses
//
// PCMCIA Slots 0,1
//
#define PXA255_BASE_REG_PA_PCMCIA_S0_IO		0x20000000
#define PXA255_BASE_REG_PA_PCMCIA_S0_ATTR	0x28000000
#define PXA255_BASE_REG_PA_PCMCIA_S0_CMN	0x2C000000
#define PXA255_BASE_REG_PA_PCMCIA_S1_IO		0x30000000
#define PXA255_BASE_REG_PA_PCMCIA_S1_ATTR	0x38000000
#define PXA255_BASE_REG_PA_PCMCIA_S1_CMN	0x3C000000
 
#define PXA255_BASE_REG_PA_DMAC		(PXA255_BASE_REG_PA_PERIPH + DMAC_OFFSET)
#define PXA255_BASE_REG_PA_FFUART	(PXA255_BASE_REG_PA_PERIPH + FFUART_OFFSET)
#define PXA255_BASE_REG_PA_BTUART	(PXA255_BASE_REG_PA_PERIPH + BTUART_OFFSET)
#define PXA255_BASE_REG_PA_I2C		(PXA255_BASE_REG_PA_PERIPH + I2C_OFFSET)
#define PXA255_BASE_REG_PA_I2S		(PXA255_BASE_REG_PA_PERIPH + I2S_OFFSET)
#define PXA255_BASE_REG_PA_AC97		(PXA255_BASE_REG_PA_PERIPH + AC97_OFFSET)
#define PXA255_BASE_REG_PA_UDC		(PXA255_BASE_REG_PA_PERIPH + UDC_OFFSET)
#define PXA255_BASE_REG_PA_STUART	(PXA255_BASE_REG_PA_PERIPH + STUART_OFFSET)
#define PXA255_BASE_REG_PA_ICP		(PXA255_BASE_REG_PA_PERIPH + ICP_OFFSET)
#define PXA255_BASE_REG_PA_RTC		(PXA255_BASE_REG_PA_PERIPH + RTC_OFFSET)
#define PXA255_BASE_REG_PA_OST		(PXA255_BASE_REG_PA_PERIPH + OST_OFFSET)
#define PXA255_BASE_REG_PA_PWM0		(PXA255_BASE_REG_PA_PERIPH + PWM0_OFFSET)
#define PXA255_BASE_REG_PA_PWM1		(PXA255_BASE_REG_PA_PERIPH + PWM1_OFFSET)
#define PXA255_BASE_REG_PA_INTC		(PXA255_BASE_REG_PA_PERIPH + INTC_OFFSET)
#define PXA255_BASE_REG_PA_GPIO		(PXA255_BASE_REG_PA_PERIPH + GPIO_OFFSET)
#define PXA255_BASE_REG_PA_PWR		(PXA255_BASE_REG_PA_PERIPH + PWR_OFFSET)
#define PXA255_BASE_REG_PA_SSP		(PXA255_BASE_REG_PA_PERIPH + SSP_OFFSET)
#define PXA255_BASE_REG_PA_MMC		(PXA255_BASE_REG_PA_PERIPH + MMC_OFFSET)
#define PXA255_BASE_REG_PA_CLK		(PXA255_BASE_REG_PA_PERIPH + CLK_OFFSET)
#define PXA255_BASE_REG_PA_NSSP		(PXA255_BASE_REG_PA_PERIPH + NSSP_OFFSET)
#define PXA255_BASE_REG_PA_HWUART	(PXA255_BASE_REG_PA_PERIPH + HWUART_OFFSET)
#define PXA255_BASE_REG_PA_LCD		(PXA255_BASE_REG_PA_PERIPH + LCD_OFFSET)
#define PXA255_BASE_REG_PA_MEMC		(PXA255_BASE_REG_PA_PERIPH + MEMC_OFFSET)


#endif  // _pxa255_base_regs_h_.