pxa255_mmc.h

老外的一个开源项目

// Copyright (c) David Vescovi.  All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation.  All rights reserved.
//------------------------------------------------------------------------------
//
//  Header: pxa255_mmc.h
//
//  Defines the clock/timer register layout and associated types and constants.
//
//------------------------------------------------------------------------------
#ifndef _PXA255_MMC_H_
#define _PXA255_MMC_H_

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
//
//  Type:  MMC_REG_T
//
//  Defines the mmc control register layout.
//
//------------------------------------------------------------------------------

typedef struct
{
	VUINT32_T	STRPC;
	VUINT32_T	STAT;
	VUINT32_T	CLKRT;
	VUINT32_T   SPI;   
	VUINT32_T   CMDAT;
	VUINT32_T   RESTO;
	VUINT32_T   RDTO;
	VUINT32_T   BLKLE;
	VUINT32_T   NOB;
	VUINT32_T   PRTBUF;
	VUINT32_T   IMASK;
	VUINT32_T   IREG;
	VUINT32_T   CMD;
	VUINT32_T   ARGH;
	VUINT32_T   ARGL;
	VUINT32_T   RES;
	VUINT32_T   RXFIFO;
	VUINT32_T   TXFIFO;
} MMC_REG_T, *PMMC_REG_T;


//
// MMC_STRPCL Bits
//
#define MMC_STRPCL_START_CLOCK			0x02
#define MMC_STRPCL_STOP_CLOCK			0x01

//
// MMC_STAT Bits
//
#define MMC_STAT_READ_TIMEOUT          (1 << 0)
#define MMC_STAT_RESPONSE_TIMEOUT      (1 << 1)
#define MMC_STAT_WRITE_DATA_CRC_ERROR  (1 << 2)
#define MMC_STAT_READ_DATA_CRC_ERROR   (1 << 3)
#define MMC_STAT_SPI_READ_TOKEN_ERROR  (1 << 4)
#define MMC_STAT_RESPONSE_CRC_ERROR    (1 << 5)
#define MMC_STAT_XMIT_FIFO_EMPTY       (1 << 6)
#define MMC_STAT_RCV_FIFO_FULL         (1 << 7)
#define MMC_STAT_CLOCK_ENABLED         (1 << 8)
#define MMC_STAT_DATA_TRANSFER_DONE    (1 << 11)
#define MMC_STAT_PROGRAM_DONE          (1 << 12)
#define MMC_STAT_END_CMD_RES           (1 << 13)

//
// MMC_CMDAT Bits
//
#define MMC_CMDAT_RESPONSE_NONE 		0x00        // no response
#define MMC_CMDAT_RESPONSE_R1   		0x01        // expected R1 response
#define MMC_CMDAT_RESPONSE_R2   		0x02        // expected R2 response
#define MMC_CMDAT_RESPONSE_R3   		0x03        // expected R3 response
#define MMC_CMDAT_DATA_EN       		(1 << 2)    // data transfer to follow
#define MMC_CMDAT_DATA_WRITE    		(1 << 3)    // data transfer is a write
#define MMC_CMDAT_STREAM        		(1 << 4)    // data transfer is stream mode
#define MMC_CMDAT_EXPECT_BUSY   		(1 << 5)    // the command uses busy signalling
#define MMC_CMDAT_INIT          		(1 << 6)    // add init clocks
#define MMC_CMDAT_DMA_ENABLE    		(1 << 7)    // enable DMA

//
// MMC_IMASK Bits
//
#define MMC_IMASK_DATA_TRAN_DONE_INT_MASKED  (1 << 0)
#define MMC_IMASK_PROG_DONE_INT_MASKED       (1 << 1)
#define MMC_IMASK_END_CMD_INT_MASKED         (1 << 2)
#define MMC_IMASK_STOP_CMD_INT_MASKED        (1 << 3)
#define MMC_IMASK_CLOCK_OFF_INT_MASKED       (1 << 4)
#define MMC_IMASK_RXFIFO_REQ_INT_MASKED      (1 << 5)
#define MMC_IMASK_TXFIFO_REQ_INT_MASKED      (1 << 6)
#define MMC_IMASK_ALL_INTERRUPTS_MASKED      (MMC_IMASK_DATA_TRAN_DONE_INT_MASKED | \
                                              MMC_IMASK_PROG_DONE_INT_MASKED      | \
                                              MMC_IMASK_END_CMD_INT_MASKED        | \
                                              MMC_IMASK_STOP_CMD_INT_MASKED       | \
                                              MMC_IMASK_CLOCK_OFF_INT_MASKED      | \
                                              MMC_IMASK_RXFIFO_REQ_INT_MASKED     | \
                                              MMC_IMASK_TXFIFO_REQ_INT_MASKED)

//
// MMC_IREG Bits
//
#define MMC_IREG_DATA_TRAN_DONE             (1 << 0)
#define MMC_IREG_PROG_DONE                  (1 << 1)
#define MMC_IREG_END_CMD                    (1 << 2)
#define MMC_IREG_STOP_CMD                   (1 << 3)
#define MMC_IREG_CLOCK_IS_OFF               (1 << 4)
#define MMC_IREG_RXFIFO_REQ                 (1 << 5)
#define MMC_IREG_TXFIFO_REQ                 (1 << 6)
#define MMC_IREG_INTERRUPTS                 0x07F

//
// MMC_PRTBUF Bits
//
#define MMC_PRTBUF_BUFFER_PARTIAL_FULL (1 << 0)

//------------------------------------------------------------------------------

#if __cplusplus
}
#endif

#endif